SUMP logic analyzer Verilog Demon core documentation

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  • Logic Sniffer Specification (Demon Core FPGA)
  • Version 1.0
  • Copyright © 2011 Ian Davis


  1. Logic Analyzer core: Introduction
  2. Logic Analyzer core: Background
  3. Logic Analyzer core: Trigger Terms
  4. Logic Analyzer core: Range Detectors
  5. Logic Analyzer core: Edge Detectors
  6. Logic Analyzer core: Timers
  7. Logic Analyzer core: Trigger Sums
  8. Logic Analyzer core: Trigger Sequence States


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