Raw 3-wire
From DP
Contents |
Overview
- Bus: general purpose 3-wire library with bitwise pin control.
- Connections: four pins (MOSI/MISO/CLOCK/CS) and ground.
- Output types: 3.3volt normal, or open drain/open collector (pull-up resistors required).
- Pull-up resistors: required for open drain output mode (2K – 10K).
- Maximum voltage: 5.5volts (5volt safe).
- Last documentation update: v5.6.
The raw 3 wire library is like SPI, but includes bitwise pin control.
Configuration options
Speed - high (~50kHz) and low (~5kHz).
Output type - open drain/open collector (high=Hi-Z, low=ground) , normal (high=3.3volts, low=ground). Use open drain/open collector output types with pull-up resistors for multi-voltage interfacing.
Syntax
| A/a/@ | Toggle auxiliary pin. Capital “A” sets AUX high, small “a” sets to ground. @ sets aux to input (high impedance mode) and reads the pin value. |
| D/d | Measure voltage on the ADC pin (v1+ hardware only). |
| W/w | Capital ‘W’ enables the on-board power supplies. Small ‘w’ disables them. (v1+ hardware only). |
| [ | Chip select (CS) active (low). |
| { | CS active (low), show the SPI read byte after every write. |
| ] or } | CS disable (high). |
| r | Read one byte by sending dummy byte (0xff). (r:1…255 for bulk reads) |
| 0b | Write this binary value. Format is 0b00000000 for a byte, but partial bytes are also fine: 0b1001. |
| 0x | Write this HEX value. Format is 0×01. Partial bytes are fine: 0xA. A-F can be lower-case or capital letters. |
| 0-255 | Write this decimal value. Any number not preceded by 0x or 0b is interpreted as a decimal value. |
| , | Value delimiter. Use a coma or space to separate numbers. Any combination is fine, no delimiter is required between non-number values: {0xa6,0, 0 16 5 0b111 0xaF}. |
| & | Delay 1uS. (&:1…255 for multiple delays) |
| (#) | Run macro, (0) for macro list |
| Bitwise | |
| ^ | Send one clock tick. (^:1…255 for multiple clock ticks) |
| / or \ | Toggle clock level high (/) and low (\). Includes clock delay (100uS). |
| - or _ | Toggle data state high (-) and low (_). Includes data setup delay (20uS). |
| ! | Read one bit with clock. |
| . | Read data pin state (no clock). |
Connections
| Bus Pirate | Dir. | Circuit | Description |
|---|---|---|---|
| MOSI | → | MOSI | Master Out, Slave In |
| MISO | ← | MISO | Master In, Slave Out |
| CS | → | CS | Chip Select |
| CLK | → | CLK | Clock signal |
| GND | ↔ | GND | Signal Ground |
