Logic Shrimp design overview
From DP
Intro and goal
features
- Features (list)
- Features
You can get a [project for $20], including worldwide shipping.
Read about the design below.
Contents |
Overview
History and related links
Hardware
Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project page.
Microcontroller
- Microcontroller
- Power and decoupling
- Oscillator
- Programming and reset support
- LEDs
SRAMs
Buffer
Signals enter the logic analyzer through a cheap and common 74xx573 transparent latch, we've used on previous logic analyzers. The input buffer does two things:
- Enables/disables the inputs
- The SRAM and PIC pins only work to 3.3volts, the buffer is 5volt tolerant
During logic recording the buffer is transparent and the input on the pins connects to the SRAM inputs. During playback, the buffer is disabled so the PIC can take control of the SRAMs.
We chose the LVx version:
- XX to XX thresholds
- XX volt tolerant
Clock system
At each pulse of the clock pin the SRAMs save a snapshot of the data on the serial input pin . The clock signal can come from two sources:
- 20MHz from the oscillator. Enabled through a 74XX125 1bit buffer
- 12MHz and less, from the PIC pulse-width modulator
The PIC configures the SRAMs to record, and then enables the clock source. The SRAMs run in a loop, always recording the state of the serial data in pin.
The active clock source drives an address counter in the PIC that tracks the current address in the SRAMs. We have to track the SRAM address on the PIC because so we know where our samples are inside the SRAM when the capture ends.
When a trigger event is detected, a second sample counter starts. This counter runs down until the configured post-trigger sample size is reached, then the PIC disables the clock source.
The PIC address counter mirrors the internal SRAM counters when sampling ends. Its value is used to calculate the address to start dumping samples.
There is an external tap for the clock signal, but it is not possible to use an external clock. An external clock would interfere with the PIC when the SRAMs are setup and dumped.
PCB
We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest designs and firmware from the project Google Code page.
- PCB and placement notes
- soldering advise
Partslist
Click for a full size placement image.
| heading | heading |
|---|---|
| cell | cell |
| cell | cell |
Firmware
The firmware is written in C and compiled with the free Microchip C18 compiler. You can download the latest files from our Google Code project page.
- Operating modes
- extra software required
We used the Microchip USB stack to run the 18F2550 as a virtual serial port. Microchip's code is open but not redistributable. If you want to compile the source, download the stack from Microchip, then drag the source code into the install directory. See the detailed instructions in the PIC compiler how-to.
.inf installation
The virtual serial port (CDC) is an open standard, it should work on any modern operating system.
You don't need a driver, but you will need a .inf file to tell Windows how to use the device. A suitable .inf is included in the project archive.
Commands
Bootloader
Source and license
Taking it further
Here's some ideas for the future:
- List
We'll post the most recent firmware updates on our blog. You can also join the discussion in the [forum].
Get one!
You can [get one for $00], including worldwide shipping.
Your purchases at Seeed Studio keep the open source project coming, we sincerely appreciate your support!
Links
- Logic Shrimp home page
- PIC 18F24J50
- 23K256 SRAM
- [ 74LVC573] 8bit buffer
- [ 74LVC125] 1bit buffer
License
- Hardware: CC-BY-SA
- Firmware: CC-BY-SA
- Bootloader: GPL