Logic Analyzer core: Timers
From DP
6. Timers
Timer limits are very simple. You write a 36 bit value. Lower 32 bits to trigger register 0x38/0x3A. Upper 4 bits to trigger register 0x39/0x3B. The fpga reference clock is 100Mhz, so each timer tick corresponds to 10ns.
Figure 17 - Timer
The 36-bit timers have a range from 10ns to 687 seconds (over 11 minutes). Timers are started, stopped, and cleared under control of the trigger sequencer.
6.1 Example (Timer Initialization)
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abap, actionscript, actionscript3, ada, apache, applescript, apt_sources, asm, asp, autoit, bash, basic4gl, blitzbasic, bnf, boo, c, c_mac, caddcl, cadlisp, cfdg, cfm, cil, cobol, cpp, cpp-qt, csharp, css, d, delphi, diff, div, dos, dot, eiffel, fortran, freebasic, genero, gettext, glsl, gml, gnuplot, groovy, haskell, html4strict, idl, ini, inno, io, java, java5, javascript, kixtart, klonec, klonecpp, latex, lisp, lotusformulas, lotusscript, lua, m68k, matlab, mirc, mpasm, mxml, mysql, nsis, objc, ocaml, ocaml-brief, oobas, oracle8, pascal, per, perl, php, php-brief, plsql, powershell, python, qbasic, rails, reg, robots, ruby, sas, scala, scheme, sdlbasic, smalltalk, smarty, sql, tcl, text, thinbasic, tsql, vb, vbnet, verilog, vhdl, visualfoxpro, winbatch, xml, xorg_conf, xpp, z80
Figure 18 - Initialize Timer Values