CoolRunner-II CPLD breakout board

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CoolRunner-II CPLD breakout board
Codename none
Status Test production
Development development forum
ID # {{{id}}}
Xc2c64a cpld breakout-vib.jpg

Ever get stuck choosing the right logic chip combination or voltage level translator? Give up the hunt and create your own custom logic chip. CPLDs can give you the logic you need, with the pinout you want, while saving board space and board revisions.

The CoolRunner-II XC2C CPLD has two separate banks of pins that can operate at different voltages, internal pull-up resistors, and pin keepers. This development board from Dangerous Prototypes will help you build your first custom logic chip using simple schematic entry, Verilog, or VHDL.

  • XC2C64A CPLD with 64 macrocells
  • On-board 1.8volt supply for the core
  • On-board 3.3volt supply for pins
  • Separate pin banks can be operated at different voltages (1.2volt to 3.3volt)
  • Selectable 1.8volt, 3.3volt, and external supply for each pin bank
  • LEDs for output
  • Push button for input
  • Populated JTAG header
  • Easy to program with the Bus Pirate and Bus Blaster
  • Open source (CC-BY-SA)




XC2C64A CPLD Breakout.png


Cct-XC2C 64a-cpld-breakout-v1a.png

Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project SVN.

CoolRunner-II XC2C64A


The XC2C64A (U1) is a 64 macrocell CPLD with two separate IO banks for voltage translation. It is one of the smallest CPLDs made by Xilinx, and is readily available from Digikey for around $2.65.

The CPLD core requires a 1.8volt supply to each VINT pin. This supply is provided by an on-board 1.8volt regulator.

The IO pins are divided into two banks that each operate from a separate supply of 1.2volts to 3.3volts. An external supply can be connected to either IO pin, or place a jumper on the V1 and V2 pins to select the on-board 1.8volt or 3.3volt power supply.

Each supply pin has a 0.1uF capacitor (C1,C2,C3,C4).

The JTAG programming pins are brought to header JT. The JTAG interface is powered by the 3.3volt core supply.

Power supply

A 1.8volt regulator (U2) powers the CPLD core and (optionally) the IO pins, which a second 3.3volt regulator (U3) is available to power the IO pin. C5, C6, C7, and C9 are 3.3uF capacitors on the regulator supply and output.

Both regulators are supplied through pin V+. The supply can be up to 5volts. Up to 100mA is available from the 3v3 pin.

LED PWR lights if the power supply is active.

Buttons and LEDs


Pinout table

BANK2 DescriptionDescription BANK1
GND Ground connection Ground connection GND
V+ Supply voltage (max 5volts) 3.3volt output (max 100mA) 3V3
V2Bank 2 IO external supply (1.2-3.3volts)1.8volt output (max 50mA) 1V8
18Push buttonBank 1 IO external supply V1
19 16
20 14
21 13
22 12
23 8
27 6
28 5
29 3
30 2
31 1
32 44
33 43
34 42
36 41
37 40
38LED D2LED D1 39



We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest board files from SVN.



Parts Quantity Value Package
C1,C2,C3,C4 4 0.1uF C603
C5,C6,C7,C9 4 3.3uF Tantalum SMC_A
D1, D2, PWR 3 Yellow LED LED-805
JTAG 1 0.1” Pin header 1X06
PB 1 SMD button, small TACT_SWITCH_SMALL
R2,R3,R4 3 2K R603
U1 1 XC2C64A_VQ44 VQ44
U2 1 1.8volt LDO voltage regulator 100mA SOT-23-5
U3 1 3.3volt LDO voltage regulator 150mA SOT-23-5
V1,V2 2 0.1” Pin header 1X03

Q1 on the bottom of the PCB is for an optional 3.3volt oscillator. It feeds into a global clock pin. Some suitable values are:


Development and programming tutorials are on the main CPLD page.

Get one!

Xc2c64a cpld breakout-vib.jpg

You can [get one for $00], including worldwide shipping.

Your purchases at Seeed Studio keep the open source project coming, we sincerely appreciate your support!



  • CC-BY-SA