Bus Blaster v2 self-test
From DP
Self test buffer, application, and instructions available here.
Overview
A way to test the Bus Blaster v2 without an actual JTAG target.
We need a better self test for the Bus Blaster v2. I think something can be done with a custom FT2232 control app and a buffer logic with loop-back cable. half the MPSSE 1 can be input, the other half output. The pins can go 0x55 0xaa and the results read from the loop-back cable from half the JTAG pins... or something.
We need to test:
- FT2232->CPLD (16 pins)
- CPLD->JTAG header (9 pins)
My proposed test is to connect every other JTAG pin with a wire, and alternate a bit pattern on it from the top 8 bits of the FTDI chips. The lower 8 bits will see the loop-back pattern. If it matches, then all is good.
There are only 4 bits of the JTAG (8 pairs, 4 write, 4 read), so it will be duplicated on the output. The input is also expected to be 8bits, if it doesn't match then the CPLD will output 0x00 to the FTDI chip.
Procedure
The JTAG pins should be connected every-other pin: TRST->TMS TDI->TCK RTCK->TDO TSRST->DBGRQ DBGACK->no connection
Test step-by-step:
- Load logic (urJTAG)
- Attach to FT2232 device
- lower 8 bits of MPSSE1 is 0xaa
- Read upper 8 bits - it should match
- Lower 8 bits is 0x55
- read upper 8 bits - it should match
CPLD
This is what the successful test is like: output 0xaa on ADBUS and read 0xAA on ACBUS. Flip it to 0x55 and verify again.
Here top and bottom 4bits of the pins from FT2232->CPLD are not the same (two pins appear stuck together). The output from the JTAG header is 0x00, and the returned value is 0x00.
Here the JTAG pins have a short and the returned byte doesn't match.