Bus Blaster v2 design overview
From DP
| Project Summary | |
|---|---|
| Name: | Bus Blaster v2 design overview |
| Buy it: | [ Get one for $35 at Seeed Studio] |
| Price: | $35 |
| Status: | Test production |
| Manufacturing: | Testing |
| Forum: | Bus Blaster v2 design overview Forum |
You can get a [Bus Blaster v2 for $35]. Bus Blaster v2 is an experimental high-speed JTAG debugger design.
- Based on FT2232H with high-speed USB 2.0
- Buffered interface works with 3.3volt to 1.2volt targets
- Reprogrammable buffer is compatible with multiple debugger types
- Compatible with 'jtagkey', 'KT-link' programmer settings in OpenOCD, urJTAG, and more
- Should support Serial Wire Debug when available
- Mini-CPLD development board: self programmable, extra CPLD pins to header
- Open source (CC-BY-SA)
Bus Blaster v2 is now available. Each unit is tested with a real JTAG target before it ships.
Read about the design below.
Contents |
Overview
The Bus Blaster is used to program and debug devices with a JTAG interface like ARM processors, CPLDs, flash memory, and more.
It has a reprogrammable buffer that can imitate buffers supported by most popular open source JTAG utilities.
This project was developed in a public forum, and progress was documented on a wiki.
Hardware
Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project page.
FT2232H
The FT2232H is a powerful USB to serial communication chip. It has an MPSSE feature that provides a simple USB to JTAG converter (and UART, I2C, or SPI). Most DIY JTAG debuggers use this chip, as do many commercial models.
Bus Blaster v1 uses the 'H' version of the chip, the latest 3.3volt revision that supports JTAG adaptive clocking. The circuit is based on a reference design from the FT2232H datasheet.
We chose not to populate the optional EEPROM on Bus Blaster v1 in order to stay within our price goals. It is not required, and without it the FT2232 uses default settings.
- See the FT2232H breakout board documentation for a complete explanation of the FT2232H reference circuit
Buffered interface
The buffer translates voltage levels between the FT2232H (3.3volts) and a JTAG device (1.2volts-3.3volts). The four main JTAG IO pins (TDI, TDO, TCK, TMS) are fixed on the FT2232, but the other reset and control pins vary among programmers.
Bus Blaster v2 is buffered by a programmable logic chip (CPLD) that can be changed to imitate many common buffer types. The CPLD is connected to the secondary JTAG interface on the FT2232, so uploading a new buffer type is done entirely from software over USB.
CPLD
An XC2C32A CoolRunner-II CPLD (IC) is used for the buffer. These are the smallest available CPLDs from Xilinx, and they only cost around $1 in onesies.
The CPLD core requires a 1.8volt supply, which is conveniently available from the FT2232. The JTAG and IO pins are powered by a separate supply between 1.2 and 3.3volts. Each supply pin gets a 0.1uF capacitor.
- For more see our CoolRunner-II quick start guide
This chip is perfect for voltage translation because the IO pins are divided into two groups that can operate from different power supplies. We connected one group to the FT2232 and the 3.3volt FT2232 power supply. The other group connects to the JTAG target, and operate from a 1.2volt to 3.3volt target supply.
You must connect the target power supply to the buffer The buffer is powered by the target, 1.2volts to 3.3volts only Connect JP4 to power the target from the programmer. 3.3volts max 200mA The buffer is NOT 5volt compatible.
We brought the extra CPLD pins to a header. The Bus Blaster v2 can also be used as a simple CoolRunner-II CPLD development board.
Buffer logic
New buffer logic is designed using simple schematic entry, Verilog, or VHDL, and the free ISE Webpack software from Xilinx.
- Learn more with our CPLD development tutorials
Here are two examples of buffer logic to give you an idea of how flexible the design can be.
See Bus Blaster v2 buffer clones for the current list of clones and programming instructions.
jtagkey
The JTAGkey is probably the most commonly used buffer configuration among FT2232-based JTAG programmers. It is compatible with OpenOCD, urJTAG, and more.
Program the Bus Blaster 2 with this buffer and it will work with most applications that support JTAGkey type programmers.
KT-link
OpenOCD and urJTAG will soon support new SWD and SWV JTAG protocols via a KT-link type buffer.
Program the Bus Blaster 2 with this buffer and it can support SWD in OpenOCD and urJTAG. Special thanks to the developers of libswd for help implementing this buffer on the Bus Blaster.
Pinout
| pin | Fixed FT2232 pin | description | direction |
|---|---|---|---|
| VTG | Voltage target | input | |
| TRST | Reset output | output | |
| TDI | ADBUS1 | JTAG data in to target | output |
| TMS | ADBUS3 | JTAG state machine update | output |
| TCK | ADBUS0 | JTAG clock in to target | output |
| RTCK | ADBUS7 | System return clock | input |
| TDO | ADBUS2 | JTAG data out from target | input |
| TSRST | Bi-directional reset pin | inout | |
| DBGRQ | Debug request | output | |
| DBGACK | Debug acknowledge | input |
PCB
We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest designs and firmware from the project Google Code page.
Partslist
Click for a full size placement image.
| Part | Quantity | Value | Package |
|---|---|---|---|
| C1-C7,C13-C21 | 16 | 100nF | C805 |
| C8 | 1 | 3.3uF | SMC_A |
| C9,C10 | 2 | 27pF | C805 |
| C11,C12,C22 | 3 | 4.7uF | SMC_A |
| IC1 | 1 | FT2232H | LQFP64 |
| IC2 | 1 | 93C46 | SOIC8 |
| IC3 | 1 | LD1117-3.3 | SOT223 |
| IC9 | 1 | XC2C32A_VQ44_2 | VQ44 |
| JP1 | 1 | 1X06 | |
| JP2 | 1 | 1X09 | |
| JP3 | 1 | 1X05 | |
| JP4 | 1 | 1X02 | |
| JTAG | 1 | 2x10 shrouded header (0.1”) | PINHEAD_-_COPY_PINSHRD_PTH_2X10 |
| L1,L2 | 2 | ferrite bead (800mA+) | FB805 |
| PWR | 1 | LED | CHIPLED_0805 |
| R1 | 1 | 12K 1% | R805 |
| R2 | 1 | 1K | R805 |
| R3,R4,R5 | 3 | 10K | R805 |
| R6 | 1 | 2.2K | R805 |
| R10 | 1 | 1K | R805 |
| USB | 1 | USB mini-B connector | CONN_USB_MINI-B |
| X1 | 1 | 12MHz crystal | 4X6 |
Taking it further
The reprogrammable buffer logic should keep this programmer from going obsolete. Already we were able to add Serial Wire Debug support by creating a new buffer implementation.
A minor revision in the next batch has a few minor changes:
- Jumper JP4 moved to edge of PCB
- LED and button connected to CPLD for demos
An eventual point revision is planned with:
- 3.3volt over voltage protection for the CPLD
- Serial resistors on the JTAG pins
v3 may use a 100pin CPLD to include support for SWV, another reduced pin-count JTAG protocol.
Get one!
[Bus Blaster v2 is now available for $35]. Each unit is tested with a real JTAG target before it ships.
Your purchases at Seeed Studio keep the open source project coming, we sincerely appreciate your support!
Links
License
Hardware license: CC-BY-SA