Bus Blaster v2 design overview
From DP
| Project Summary | |
|---|---|
| Name: | Bus Blaster v2 design overview |
| Buy it: | [ Get one for $35 at Seeed Studio] |
| Price: | $35 |
| Status: | Test production |
| Manufacturing: | Testing |
| Forum: | Bus Blaster v2 design overview Forum |
You can get a [Bus Blaster v2 for $35]. Bus Blaster v2 is an experimental high-speed JTAG debugger design.
- Based on FT2232H with high-speed USB 2.0
- Buffered interface works with 3.3volt to 1.2volt targets
- Reprogrammable buffer (CPLD) works with OpenOCD, urJTAG, and more
- Compatible with 'jtagkey', 'KT-link', other programmer types
- Should support Serial Wire Debug with KT-link compatible interface
- Open source (CC-BY-SA)
Bus Blaster v2 is now available. Each unit is tested with a real JTAG target before it ships.
Read about the design below.
Contents |
Overview
The Bus Blaster is used to program and debug devices with a JTAG interface like ARM processors, CPLDs, flash memory, and more.
It has a reprogrammable buffer that can imitate buffers supported by most popular open source JTAG utilities.
This project was developed in a public forum, and progress was documented on a wiki.
Hardware
Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project page.
FT2232H
The FT2232H is a powerful USB to serial communication chip. It has an MPSSE feature that provides a simple USB to JTAG converter (and UART, I2C, or SPI). Most DIY JTAG debuggers use this chip, as do many commercial models.
Bus Blaster v1 uses the 'H' version of the chip, the latest 3.3volt revision that supports JTAG adaptive clocking. The circuit is based on a reference design from the FT2232H datasheet.
We chose not to populate the optional EEPROM on Bus Blaster v1 in order to stay within our price goals. It is not required, and without it the FT2232 uses default settings.
- See the FT2232H breakout board documentation for a complete explanation of the FT2232H reference circuit
Buffered interface
The buffer translates voltage levels between the FT2232H (3.3volts) and a JTAG device (1.2volts-3.3volts). The buffer is the primary difference between the Bus Blaster and a plain FT2232H development board.
The buffer is powered by the target, 1.2volts to 3.3volts only You must connect the target power supply to the JTAG VTG pin
The four main JTAG IO pins (TDI, TDO, TCK, TMS) are at fixed locations on the FT2232, but the other control pins vary among programmers.
Bus Blaster v2 uses a programmable logic chip (CPLD) that can be changed to imitate many common buffer types. The CPLD is connected to the secondary JTAG interface on the FT2232, so uploading a new buffer type is done entirely from software over USB.
When written, we had buffer logic compatible with:
- JTAGkey
- KT-link
- All buffer logic
We brought the extra CPLD pins to a header. The Bus Blaster v2 can also be used as a simple CoolRunner-II CPLD development board.
- JP4 can be used to power the target from the programmer, with up to 200mA of 3.3volts.
The buffer is NOT 5volt compatible.
Pinout
| pin | FT2232 pin | description | direction |
|---|---|---|---|
| TDI | ADBUS1 | JTAG data in to target | output |
| TCK | ADBUS0 | JTAG clock in to target | output |
| TMS | ADBUS3 | JTAG state machine update | output |
| TRST | ACBUS0 | Reset output | output |
| TSRST | ACBUS1 | Bi-directional reset pin | output |
| DGBRQ | ACBUS4 | Debug request | output |
| TDO | ADBUS2 | JTAG data out from target | input |
| TSRST | ADBUS6 | Bi-directional reset pin | input |
| RTCK | ADBUS7 | System return clock | input |
| DGBACK | ACBUS5 | Debug acknowledge | input |
| VTG | ADBUS5 | Voltage target | input |
PCB
File:Bus-blaster-v2-pcb-scan-490.jpg
We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest designs and firmware from the project Google Code page.
Partslist
Click for a full size placement image.
| Part | Quantity | Value | Package |
|---|---|---|---|
| C1-C7,C13-C21 | 16 | 100nF | C805 |
| C8 | 1 | 3.3uF | SMC_A |
| C9,C10 | 2 | 27pF | C805 |
| C11,C12,C22 | 3 | 4.7uF | SMC_A |
| IC1 | 1 | FT2232H | LQFP64 |
| IC2 | 1 | 93C46 | SOIC8 |
| IC3 | 1 | LD1117-3.3 | SOT223 |
| IC9 | 1 | XC2C32A_VQ44_2 | VQ44 |
| JP1 | 1 | 1X06 | |
| JP2 | 1 | 1X09 | |
| JP3 | 1 | 1X05 | |
| JP4 | 1 | 1X02 | |
| JTAG | 1 | PINHEAD_-_COPY_PINSHRD_PTH_2X10 | |
| L1,L2 | 2 | FB805 | |
| PWR | 1 | CHIPLED_0805 | |
| R1 | 1 | 12K 1% | R805 |
| R2 | 1 | 1K | R805 |
| R3,R4,R5 | 3 | 10K | R805 |
| R6 | 1 | 2.2K | R805 |
| R10 | 1 | 470 | R805 |
| USB | 1 | CON-USB-MINI-BUSB1 | CONN_USB_MINI-B |
| X1 | 1 | 12MHz | 4X6 |
Taking it further
The reprogrammable buffer logic should keep this programmer from going obsolete. Already we were able to add Serial Wire Debug support by creating a new buffer implementation.
A minor revision in the next batch has a few minor changes:
- Jumper JP4 moved to edge of PCB
- LED and button connected to CPLD for demos
An eventual point revision is planned with:
- 3.3volt over voltage protection for the CPLD
- Serial resistors on the JTAG pins
v3 may use a 100pin CPLD to include support for SWV, another reduced pin-count JTAG protocol.
Get one!
[Bus Blaster v2 is now available for $35]. Each unit is tested with a real JTAG target before it ships.
Your purchases at Seeed Studio keep the open source project coming, we sincerely appreciate your support!
Links
License
Hardware license: CC-BY-SA