Bus Blaster v1 design

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Proto-bus blaster.jpg

High-speed JTAG debugger, flash ROM programmer.

  • compatible with OpenOCD and urJTAG as 'jtagkey'
  • 3.3volt-1.2volt IO buffer
  • open source

You can get a [Bus Blaster v1 for $30].

Read about the design below.

Contents

Overview

The Bus Blaster is used to program and debug devices with a JTAG interface. It has a Amontec JTAGkey-compatible interface that supported by the most popular open source JTAG apps.

This project was developed in a public forum, and progress was documented on a [Ricet:_Bus_Blaster_v1|wiki]].

Hardware

Project-schematic.png

Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project page.

FT2232H

Project-section-diagram-490.jpg

  • Chip, crystal, reset, power supply
  • See FT2232H breakout board documentation

Buffer interface

Project-section-diagram-490.jpg

The four main JTAG IO pins () are fixed on the FT2232.

The buffer control pins vary by programmer type. We wanted the Bus Blaster to work 'out of the box', so we make our buffer interface compatible with the Amontec JTAGkey.

Busblasterjtagcon-updated.png

We reverse engineered the JTAGkey connections from the OpenOCD source code and the Openmoko debug board v3 schematics.

Outputs

Outputs (FT2232->buffer)
pin IO pinFT2232 pin description Enable pinnotes
TDI Data in to targetJTAG_BUF_EN Shared output enable
TCK ClockJTAG_BUF_EN Shared output enable
TMS Machine stateJTAG_BUF_EN Shared output enable
TSRSTTSRST_BUF_ENIndividual output enable, connected to TSRST input
TRSTTRST_BUF_ENIndividual output enable
DGBRQDebug request

This buffer is difficult to choose because it requires three different output enables. A chip like the 74LVC8T245 (1.6volt to 5volts) has a single output enable for 8bits - we'd need three and 19 pins would be wasted.

The 74xx4T245 commonly used on other FT2232 programmers to give 1.6-5volt output won't work for us because the new FT2232H is 3.3volts instead of 5volts.

We used the SN74AVC4T245, which gives 1.2volt-3.6volt output range. Ideally, a 5volt part can be found in the future.

Inputs

Inputs (buffer->FT2232)
pin IO pinFT2232 pindescription notes
TDOData out from target
TSRST Connected to TSRST output
RTCKReturn clock For adaptive clocking
DGBACKDebug acknowledge
VTGVoltage target detectSimple transistor with pullup resistor, inverts signal

Two interchangable buffers:

PCB

File:Project-render-490.jpg

We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest designs and firmware from the project Google Code page.

  • PCB and placement notes
  • soldering advise

Partslist

490px

Click for a full size placement image.

partlist
heading heading
cell cell
cell cell

Taking it further

We're already hard at work on Bus Blaster v2. The updated design uses a CPLD instead of discrete buffer chips, it will be cheaper and more flexible.

We'll post the most recent firmware updates on our blog. You can also join the discussion in the [forum].

Get one!

You can [get one for $00], including worldwide shipping.

Your purchases at Seeed Studio keep the open source project coming, we sincerely appreciate your support!

Links

License

Hardware license: CC-BY-SA