Xilinx Spartan 3 FPGA quick start

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Contents

Features

  • 1.2volt to 3.3volt IO, additional core (1.2volt) and auxiliary (2.5volt) supplies required
  • Spartan-3A - volatile configuration (must be programmed every power-up)
  • Spartan-3AN - static configuration, more expensive
  • Available at Digikey, among others

Development and programming

Xilinx has a free FPGA and CPLD development package called ISE WebPack. This is the only development tool we're aware of.

JTAG cables

Spartan 3 uses a JTAG programming interface.

  • Parallel cable and ISE
  • FT2232 JTAG

Loaders

Load configurations into the CPLD or FPGA by 'playing' an (X)SVF encoded file with a JTAG cable.

  • UrJTAG - load SVF with a number of programmers, including common FT2232 programmers
  • OpenOCD - detects FPGA/CPLDs, but doesn't do much with them

Basic circuit

Quick-FPGA-Spartan3-basic-circuit.png

Power

Requires a minimum of two supplies.

  • 1.2volts - core supply
  • 2.5volts - auxiliary supply for JTAG, reset, status, and configuration pins
  • 1.2volts-3.3volts - IO supply for the IO pins, use your preferred interface voltage

Reset

  • INIT_B - FPGA master reset, 4.7K pull-up to VCC02 (3.3volts) for normal operation
  • PROG_B - FPGA programming mode, 4.7K pull-up to VAUX (2.5volts) for normal operation
  • DONE - Goes high when FPGA finishes loading, requires 330ohm pull-up to VAUX (2.5volts)
  • HSWAP - Low enables pull-ups to VCCO (bank voltage) on all pins during configuration and start up. Tie high to VCCO with a 560ohm resistor to disable

Boot configuration

MS2, MS1, MS0 select the startup configuration. These pins tell the FPGA where to load it's configuration.

Spartan-3E Configuration Mode Options and Pin Settings
M[2:0] mode pin settings Data width Configuration memory source Clock source Total I/O pins borrowed during configuration Configuration mode for downstream daisy-chained FPGAs
Master Serial <0:0:0> Serial Xilinx Platform Flash Internal oscillator 8 Slave Serial
SPI <0:0:1> Serial Industry-standard SPI serial Flash Internal oscillator 13 Slave Serial
BPI <0:1:0>=Up <0:1:1>=Down Byte-wide Industry-standard parallel NOR Flash or Xilinx parallel Platform Flash Internal oscillator 46 Slave Parallel
Slave Parallel <1:1:0> Byte-wide Any source via microcontroller, CPU, Xilinx parallel Platform Flash, etc. External clock on CCLK pin 21 Slave Parallel or Memory Mapped
Slave Serial <1:1:1> Serial Any source via microcontroller, CPU, Xilinx Platform Flash, etc. External clock on CCLK pin 8 Slave Parallel
JTAG <1:0:1> Serial Any source via microcontroller, CPU, System ACE CF, etc. External clock on TCK pin 0 JTAG

Boot from ROM

Quick-FPGA-Spartan3-load-from-ROM.png

In a fixed design it's convenient to store the FPGA configuration in an external ROM chip so it loads automatically.

Number of Bits to Program a Spartan-3E FPGA (Uncompressed Bitstreams)
Spartan-3E FPGA Number of Configuration Bits
XC3S100E 581,344
XC3S250E 1,353,728
XC3S500E 2,270,208
XC3S1200E 3,841,184
XC3S1600E 5,969,696

VS2, VS1, VS0 select the ROM protocol used.

Variant Select Codes for Various SPI Serial Flash PROMs
VS2 VS1 VS0 Dummy Bytes SPI Serial Flash Vendor SPI Flash Family
1 1 1 FAST READ (0x0B) see Figure 53 1 STMicroelectronics (ST) Atmel Intel Spansion (AMD, Fujitsu) Winbond (NexFlash) Macronix Silicon Storage Technology (SST) Programmable Microelectronics Corp. (PMC) AMIC Technology Eon Silicon Solution, Inc. M25Pxx M25PExx M45PExx AT45DB 'D'-Series Data Flash AT26/AT25 S33 S25FLxxxA NX25/W25 MX25Lxxxx SST25LFxxxA SST25VFxxxA Pm25LVxxx A25L EN25
1 0 1 READ (0x03) see Figure 53 0 STMicroelectronics (ST) Spansion (AMD, Fujitsu) Winbond (NexFlash) Macronix Silicon Storage Technology (SST) Programmable Microelectronics Corp. (PMC) M25Pxx M25PExx M45PExx S25FLxxxA NX25/W25 MX25Lxxxx SST25LFxxxA SST25VFxxxA SST25VFxxx Pm25LVxxx

JTAG programming

  • Must be programmed after every power cycle if not a static FPGA
  • Common Xilinx JTAG pinout
  • 2.5volts on the Spartan 3!!

Clock source

Connect to a GCK pin

Peripherals

IO

  • Pin current depends on the power supply and acceptable voltage levels, though roughly 8mA (ideal) to 20mA (acceptable) should be possible
  • The chip is divided into banks that each accept an independent supply from 1.2volts to 3.3volts. Feed the supply to the IOx supply pin
  • Pins have "bus hold" feature that gently pulls the pin to the current input value (up or down), uses less current than a pull-up resistor
  • Bus hold or pull-up resistors (not both) can be applied globally to all pins. The bus hold or pull-up can then be disabled on individual pins

There are also some pins with special features, though they are not used unless specifically enabled in the FPGA synthesis:

  • GCK (global clock) - optimized to distribute a clock signal with minimum skew and extra resources
  • GSR (global set reset) - optimized path to the Set/Reset signal, allows synchronous reset of the flip-flop in all cells with minimum extra resources
  • GTS (global tri-state) - optimized to put all FPGA pins in a high impedance state

DCM

Clock handling modules

Resources