XT IDE disk controller

From DP

Overview

"The XT-IDE project is a Vintage Computer forum driven project to develop and manufacturer an 8-bit ISA IDE controller. It allows any PC/XT class machine to use modern IDE hard drives or Compact Flash devices for long term storage." (From the XTIDE project wiki)

Our version of the XTIDE controller replaces the 7400-series logic chips with a CPLD, a chip that can be programmed to replace dozens of individual logic chips. The logic is designed in software by drawing a schematic, and then uploaded to the CPLD. New logic circuits can be designed and tested without making new hardware each time.

V2 has been built and tested, it works! Thanks Pietja!

We have free PCBs available if you'd like to build your own!

XTIDE project. Original design, bios, drivers, etc
Our project files. XTIDE with CPLD, CPLD logic implementation
XTIDE-CPLD changelog
Dangerous Prototypes V2 Compatibility Notes. Compatibility test results of the DPv2 board with XTIDE Universal BIOS v1.15

Prototypes

V1 and v2 have been tested and work!

v2

All discrete logic chips are now integrated into a single CPLD programmable logic chip.

v1

V1 tests the use of a CPLD to replace some of the discrete logic chips.

Version 1a has been tested. It works with a few minor modifications.

V1a is the only version cut correctly. It uses 3.3volt CPLD
V1a build thread

Version 1a bugs:

In both PCB's (v1 and v1a) the "8bit<->16bit IDE mux" is not connected to the CPLD. 5 jumper wires are needed.

Downloads

Programming and testing

Here are the links to the SVN to program the CPLD with an Bus Pirate:

The bios for the card can be found here, be sure to read the wiki there on how to configure the bios and program the EEPROM with the xtidecfg.com program.

Benchmarking: a simple test utility (be sure to set buffers=99 in config.sys). Results.

The "Chuck mod" performance enhancement can be done just by programming new logic into the CPLD with the flowing files:

Benchmarks

V1:

Write Speed : 213,99 KB/s
Read Speed : 248,67 KB/s
8K random, 70% read : 21,20 IOPS
Sector random read : 60,37 IOPS
Average seek, including latency, is 17,17 ms.

V2:

Write Speed : 214,06 KB/s
Read Speed : 243,11 KB/s
8K random, 70% read : 21,15 IOPS
Sector random read : 65,05 IOPS
Average seek, including latency, is 15,67 ms.

Source.

DIP switch settings

IO RANGE DIP SW 1:4	Memory Address DIP SW 5:8
1111 = 200h	1111 = C0000 - C1FFF
1110 = 220h	1110 = C4000 - C5FFF
1101 = 240h	1101 = C8000 - C9FFF
1100 = 260h	1100 = CC000 - CDFFF
1011 = 280h	1011 = D0000 - D1FFF*
1010 = 2A0h	1010 = D4000 - D5FFF
1001 = 2C0h	1001 = D8000 - D9FFF
1000 = 2E0h	1000 = DC000 - DDFFF
0111 = 300h*	0111 = E0000 - E1FFF
0110 = 320h	0110 = E4000 - E5FFF
0101 = 340h	0101 = E8000 - E9FFF
0100 = 360h	0100 = EC000 - EDFFF
0011 = 380h	0011 = F0000 - F1FFF
0010 = 3A0h	0010 = F4000 - F5FFF
0001 = 3C0h	0001 = F8000 - F9FFF
0000 = 3E0h	0000 = FC000 - FDFFF

0 = OFF 1 = ON *Default Setting

Latest Schematic

Early schematics

PCB

V2

V1b

V1a (PCB cut correctly, uses 3.3volt CPLD

V1 (PCB not cut for XT slot, uses 3.3volt CPLD)
VX Not shown, but files are in SVN (PCB not cut, uses 5.0volt CPLD)

Click for a full size placement image.

Partlist

partlist
Part	Quantity	Value	Package
C1,C3,C4,C5,C7	5	0.1uF	C0603
C2	1	47uF	SANYO-OSCON_SMD_A5
C6	1	1uF	C0603
DIP_SW	1		EDG-08
H1,H2	2	MOUNT-PAD-ROUND3.6	3,6-PAD
IC1	1	28C64AP	DIL28-6
IC2	1	74HC688DW	SO20W
IC3,IC4	2	74HCT573D	SO20W
IC5	1	74HCT245DW	SO20W
IC6	1	XC9572VQ44*	VQ44
IDE	1		MA20-2
JP1	1	ROM ENABLE	1X02-S
JP2	1	WRITE ENABLE	1X02-S
JP3	1	IRQ_SELECT	2X05
JP4	1	CSEL	1X03-S
JP6	1	JTAG	1X06-S
JP7	1	HD_LED	1X02-S
LED1	1		CHIPLED_0805
R1,R2	2		R0603
R3,R4,R5,R6	4	10k	R0603
R7	1	151	R0603
RN1	1	10k	SIL9
RN2	1		SIL9
ST1	1		IBM8BIT
U$3,U$7	2		JUMP2_DESC_OFF
U$4	1		JUMP3_DESC_LEFT
U$5	1		JUMP3_DESC_RIGHT
U$6,WRITE_ENABLE	2		JUMP2_DESC_ON
VR1	1	MIC5205-3.3YM5	SOT-23-5