XT IDE disk controller

From DP

Jump to: navigation , search

Prototype-XTIDE-controller-CPLD-v2.jpg

Contents

Overview

"The XT-IDE project is a Vintage Computer forum driven project to develop and manufacturer an 8-bit ISA IDE controller. It allows any PC/XT class machine to use modern IDE hard drives or Compact Flash devices for long term storage." (From the XTIDE project wiki)

Our version of the XTIDE controller replaces the 7400-series logic chips with a CPLD, a chip that can be programmed to replace dozens of individual logic chips. The logic is designed in software by drawing a schematic, and then uploaded to the CPLD. New logic circuits can be designed and tested without making new hardware each time.

V2 has been built and tested, it works! Thanks Pietja!

We have free PCBs available if you'd like to build your own!

Prototypes

V1 and v2 have been tested and work!

v2

Prototype-XTIDE-control1er-CPLD-v2.jpg

Prototype-XTIDE-controller-CPLD-v2.jpg

All discrete logic chips are now integrated into a single CPLD programmable logic chip.

v1

Prototype-XTIDE-controller-CPLD.jpg

V1 tests the use of a CPLD to replace some of the discrete logic chips.

Version 1a has been tested. It works with a few minor modifications.

Version 1a bugs:

Downloads

Programming and testing

Here are the links to the SVN to program the CPLD with an Bus Pirate:

The bios for the card can be found here, be sure to read the wiki there on how to configure the bios and program the EEPROM with the xtidecfg.com program.

Benchmarking: a simple test utility (be sure to set buffers=99 in config.sys). Results.

The "Chuck mod" performance enhancement can be done just by programming new logic into the CPLD with the flowing files:

Benchmarks

V1:

  • Write Speed : 213,99 KB/s
  • Read Speed : 248,67 KB/s
  • 8K random, 70% read : 21,20 IOPS
  • Sector random read : 60,37 IOPS
  • Average seek, including latency, is 17,17 ms.

V2:

  • Write Speed : 214,06 KB/s
  • Read Speed : 243,11 KB/s
  • 8K random, 70% read : 21,15 IOPS
  • Sector random read : 65,05 IOPS
  • Average seek, including latency, is 15,67 ms.

Source.

DIP switch settings

IO RANGE
DIP SW 1:4
Memory Address
DIP SW 5:8
1111 = 200h 1111 = C0000 - C1FFF
1110 = 220h 1110 = C4000 - C5FFF
1101 = 240h 1101 = C8000 - C9FFF
1100 = 260h 1100 = CC000 - CDFFF
1011 = 280h 1011 = D0000 - D1FFF*
1010 = 2A0h 1010 = D4000 - D5FFF
1001 = 2C0h 1001 = D8000 - D9FFF
1000 = 2E0h 1000 = DC000 - DDFFF
0111 = 300h*0111 = E0000 - E1FFF
0110 = 320h 0110 = E4000 - E5FFF
0101 = 340h 0101 = E8000 - E9FFF
0100 = 360h 0100 = EC000 - EDFFF
0011 = 380h 0011 = F0000 - F1FFF
0010 = 3A0h 0010 = F4000 - F5FFF
0001 = 3C0h 0001 = F8000 - F9FFF
0000 = 3E0h 0000 = FC000 - FDFFF

0 = OFF 1 = ON *Default Setting


Latest Schematic

Cct-CPIDE-44vqfp-v1a.png

Early schematics

Cct-CPIDE-44vqfp.png

PCB

Pcb-XT-IDE-adapter-v2.jpg

  • V2

Pcb-XT-IDE-adapter-v1b.jpg

  • V1b


Pcb-XT-IDE-adapter.jpg

  • V1a (PCB cut correctly, uses 3.3volt CPLD

Pcb-xtide.jpg

  • V1 (PCB not cut for XT slot, uses 3.3volt CPLD)
  • VX Not shown, but files are in SVN (PCB not cut, uses 5.0volt CPLD)

Click for a full size placement image.

Partlist

CPIDE-44vqfp-v1a-brd.png

CPIDE-44vqfp.brd.png


partlist
PartQuantityValuePackage
C1,C3,C4,C5,C750.1uFC0603
C2147uFSANYO-OSCON_SMD_A5
C611uFC0603
DIP_SW1EDG-08
H1,H22MOUNT-PAD-ROUND3.63,6-PAD
IC1128C64APDIL28-6
IC2174HC688DWSO20W
IC3,IC4274HCT573DSO20W
IC5174HCT245DWSO20W
IC61XC9572VQ44*VQ44
IDE1MA20-2
JP11ROM ENABLE1X02-S
JP21WRITE ENABLE1X02-S
JP31IRQ_SELECT2X05
JP41CSEL1X03-S
JP61JTAG1X06-S
JP71HD_LED1X02-S
LED11CHIPLED_0805
R1,R22R0603
R3,R4,R5,R6410kR0603
R71151R0603
RN1110kSIL9
RN21SIL9
ST11IBM8BIT
U$3,U$72JUMP2_DESC_OFF
U$41JUMP3_DESC_LEFT
U$51JUMP3_DESC_RIGHT
U$6,WRITE_ENABLE2JUMP2_DESC_ON
VR11MIC5205-3.3YM5SOT-23-5

CPLD logic

Top level logic

  • V1

Top v1.png

  • V1 with Chuck mod

Top v1 Chuck mod.png

  • V2

Top v2.png

  • V2 with Chuck mod

Top v2 Chuck mod.png


Second level logic blocks

  • IDE Address Decoding

IDE DECODE.png

  • ROM Address Decoding

ROM DECODE.png

  • 8bit to 16bit IDE mux

IDE MUX 8bit 16bit.png


First version CPLD logic

XT-IDE-CPLD-.png

  • XTIDE drive logic implemented in the CPLD
  • Software is free ISE Webpack

Design tests

XT-IDE-logic-chips.pngXT-IDE-84plcc.pngXT-IDE-44tqfp.png

Errors

XTIDE-CPLD-3V3-v1b-disconnect.png


XTIDE-CPLD-5V-v1b-disconnect.png

License