SUMP logic analyzer Verilog Demon core documentation

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  • Logic Sniffer Specification (Demon Core FPGA)
  • Version 1.0
  • Copyright © 2011 Ian Davis

Contents

  1. Logic Analyzer core: Introduction
  2. Logic Analyzer core: Background
  3. Logic Analyzer core: Trigger Terms
  4. Logic Analyzer core: Range Detectors
  5. Logic Analyzer core: Edge Detectors
  6. Logic Analyzer core: Timers
  7. Logic Analyzer core: Trigger Sums
  8. Logic Analyzer core: Trigger Sequence States

License

This document is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This document is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this document; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA