Ricet: Bus Blaster v1

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Ricet: Bus Blaster v1
Codename Ricet
Status Test production
Development development forum
ID # {{{id}}}

High-speed JTAG debugger, flashrom programmer.

Contents

Development

Forum

Goals

  • High-speed programmer debugger for JTAG and ROM chips


Software

  • UrJTAG programming FPGAs, CPLDs, more with XSVF
  • OpenOCD debugging ARM chips, mostly

Prototypes

Proto-bus blaster.jpg

BusBlaster-debug.jpg

BusBlaster-testing-cpld.jpg

BusBlaster-brd.jpg Blaster-FT232-brd.jpg

JTAG pin connections

Busblasterjtagcon-updated.png

Pin connection compatibility

Bus Blaster pin connection comparison
JTAG signalDirectionBus Blaster Amontec JTAGkeyOpenmoko debugOpenOCDLink
TDI out ADBUS1ADBUS1ADBUS1
TMS out ADBUS3 ADBUS3 ADBUS3
TCK out ADBUS0 ADBUS0 ADBUS0
TDOinADBUS2ADBUS2ADBUS2
JTAG BUF ENoutADBUS4ADBUS4n/a
nTRSToutACBUS0ACBUS0ACBUS1
nTRST_BUF_ENoutACBUS2ACBUS2ACBUS0
nSRSToutACBUS1ACBUS1ACBUS3
nSRST_BUF_ENoutACBUS3ACBUS3ACBUS2
nSRSTinADBUS6ADBUS6n/a
RTCKinADBUS7n/a (ADBUS7 reserved input)connected to JTAG pin 13
DBGACKinACBUS5n/an/a
DBGRQoutACBUS4n/an/a
Target present(inverted)inADBUS5ADBUS5n/a

BOLD signals are fixed FT2232 pins.

JTAGkey buffer connections:

  • nTRST = 0x01; (ACBUS0)
  • nTRSTnOE = 0x4; (ACBUS2)
  • nSRST = 0x02; (ACBUS1)
  • nSRSTnOE = 0x08; (ACBUS3)

References

Outputs

Outputs (FT2232->buffer)
pin IO pinFT2232 pin description Enable pinnotes
TDI Data in to targetJTAG_BUF_EN Shared output enable
TCK ClockJTAG_BUF_EN Shared output enable
TMS Machine stateJTAG_BUF_EN Shared output enable
TSRSTTSRST_BUF_ENIndividual output enable, connected to TSRST input
TRSTTRST_BUF_ENIndividual output enable
DGBRQDebug request

This buffer is difficult to choose because it requires three different output enables. A chip like the 74LVC8T245 (1.6volt to 5volts) has a single output enable for 8bits - we'd need three and 19 pins would be wasted.

The 74xx4T245 commonly used on other FT2232 programmers to give 1.6-5volt output won't work for us because the new FT2232H is 3.3volts instead of 5volts.

We used the SN74AVC4T245, which gives 1.2volt-3.6volt output range. Ideally, a 5volt part can be found in the future.

Inputs

Inputs (buffer->FT2232)
pin IO pinFT2232 pindescription notes
TDOData out from target
TSRST Connected to TSRST output
RTCKReturn clock For adaptive clocking
DGBACKDebug acknowledge
VTGVoltage target detectSimple transistor with pullup resistor, inverts signal

Two interchangable buffers:

Resources

Reverse engineering links

Schematic

BusBlaster.png

Ft2232.png

PCB

Blaster-board.png


JTAG pinout

20pin-jtag-cct.png

Partlist

BusBlaster.brd
PartQuantityValuePackage
C11100nFC805
C21100nFC805
C31100nFC805
C41100nFC805
C51100nFC805
C61100nFC805
C71100nFC805
C813.3uFSMC_A
C9127pFC805
C10127pFC805
C1114.7uFSMC_A
C1214.7uFSMC_A
C131100nFC805
C141100nFC805
C151100nFC805
C161100nFC805
C171100nFC805
C181100nFC805
C191100nFC805
C201100nFC805
C211100nFC805
C2214.7uFSMC_A
C251100nFC805
IC11FT2232HLQFP64
IC2193C46SOIC8
IC31LD1117-3.3SOT223
IC41SN74AVC4T245TSSOP16
IC51SN74AVC4T245TSSOP16
IC61SN74LVC2T45DCTRDCT_R_PDSO_G8
IC71SN74LVC2T45DCTRDCT_R_PDSO_G8
IC81SN74LVC2T45DCTRDCT_R_PDSO_G8
JTAG12520-PAK100/2500-20
L11FB805
L21FB805
LED11CHIPLED_0805
LED21CHIPLED_0805
PROG11X05
R1112KR805
R211KR805
R3110KR805
R4110KR805
R5110KR805
R612.2KR805
R7110KR805
R81100kR805
R911kR805
R101470R805
R111470R805
T11SOT23-BEC
USB1MINI-USBMINI-USBB
X11CRYSTAL_212M_4X6

Testing

Openocd-chain1.png

Openocd-chain2.png

Openocd-chain3.png


Busblaster-chain-scan.png

Busblaster-working.png


busblaster.cfg file for OpenOCD

#
# Bus Blaster
#
# http://dangerousprototypes.com/docs/Bus_Blaster
#

interface ft2232
ft2232_device_desc "Dual RS232-HS"
ft2232_layout jtagkey
ft2232_vid_pid 0x0403 0x6010
openocd -f busblaster.cfg

Example usage.

openocd.cfg for OpenOCD

source [find busblaster.cfg]
jtag_khz 2000
openocd -f openocd.cfg

Example usage (required busblaster.cfg).