Logic Sniffer firmware overview
What the firmware in the PIC does:
- At start PIC holds PROG_B low to keep the FPGA reset
- PIC measures voltages and does some self-test sanity checks
- PIC opens a SPI connection to the ROM chip
- PIC reads the JEDEC ID from the ROM chip over SPI connection, this tells it if the ROM is alive
- PIC tears down the SPI connection to the ROM and releases PROG_B. The FPGA now starts on an internal clock and loads the bitstream from the ROM. Interesting tidbit: the FPGA keeps looking forever if the ROM is dead, noticed this on a LA output.
- PIC watches the DONE line from the FPGA (ACT LED blinks), when it goes high the FPGA is done loading (ACT LED off). If it never goes high, the PIC times out and goes to update mode (ACT LED on)
- PIC opens a SPI connection to the FPGA. This is normal 4-wire, plus a dataready flag. The PIC controls CS and the clock, and is the master. However, the dataready flag gives the FPGA data priority.
- Data from the FPGA has priority. When the Dataready flag is high the PIC reads data from the FPGA and writes it to the USB. If you don't read while dataready is high, the data is lost.
- When there is data from USB, and if the dataready flag is low, it gets written to the FPGA over SPI.