Logic Shrimp v2 design overview

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Project Summary
Name: Logic Shrimp v2 design overview
Buy it: [ Get one for {{{price}}} at Seeed Studio]
Price: {{{price}}}
Status: Prototyping
Manufacturing: Testing
Forum: [ Logic Shrimp v2 design overview Forum]
File:Logic-shrimp-v2-inuse.jpg
  • About/feature list
  • SUMP protocol compatible
  • USB interface, USB firmware upgradable
  • Open source (CC-BY-SA)

Available for $xx at Seeed Studio.

Read about the design below.

Contents

Overview

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About/history

Hardware

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Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project page.

Microcontroller

File:Logic-shrimp v2-microcontro .jpg

A PIC 18F24J50 (IC5), the 3.3volt version of the famous 18F2550 USB family, is the microcontroller for this project. The PIC handles the USB connection, the SUMP protocol interface, and configures the SRAMs to capture logic signals.

This chip is an extended life product and should be available for many years in the future.

  • C1 and C4 (0.1uF) are small capacitors on the supply pins for decoupling
  • C11 is a 10uF tantalum capacitor for the 2.5volt core regular inside the PIC
  • The PIC is programmed though the ICSP header, resistor R4 holds the programming/reset pin high for normal operation
  • 20MHz oscillator Q2 is the clock source for the PIC
  • ACT is an indicator LED
  • The entire circuit is powered by 3.3volt regulator VR1, with supply capacitors C12 (10uF) and C10 (1uF)

SRAM

File:Logic-shrimp-v2-sram.jpg

abut the SRam

Buffer

File:Sch-Logic-Shrimp-v2-buffer .png

  • about the buffer

Clock system

File:Sch-Logic-Shrimp-v2-clock-.png

  • about the clk

PCB

File:Logic-shrimp-v2-pcb.jpg

We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest designs and firmware from the project Google Code page.

Partslist

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Click for a full size placement image.

  • partlist table

The latest sources and distributors are in the master partlist. See something missing? Please let us know.

Firmware

The Logic Shrimp supports a sub-set of the SUMP logic analyzer protocol.

The firmware is written in C and compiled with the free Microchip C18 compiler. You can download the latest files from our Google Code project page.

We used the Microchip USB stack to run the 18F24J50 as a virtual serial port. Microchip's code is open but not redistributable. If you want to compile the source, download the stack from Microchip, then drag the source code into the install directory. See the detailed instructions in the PIC compiler how-to.

.inf installation

The virtual serial port (CDC) is an open standard, it should work on any modern operating system.

You don't need a driver, but you will need an .inf file to tell Windows how to use the device. A suitable .inf is included in the project archive.

Bootloader

Easy firmware updates over USB are possible using the Diolan USB HID bootloader. Multi-platform update utilities are included in the project archive.

Taking it further

V1 of the firmware is extremely simple, there's lots of room for new features.

  • The triggers leave a lot to be desired
  • Frequency and signal generator features can be added by recording to the SRAMs and replaying

In a v2 hardware update we'd like to replace both buffer chips with a CPLD. The CPLD could also support advanced triggering not possible with the PIC.

We'll post the most recent firmware updates on our blog. You can also join the discussion in the forum.

Get one!

File:Logic-shrimp-v2.jpg

You can get a Logic Shrimp for $34.90 only at Seeed Studio.

Your purchases at Seeed Studio keep the open source project coming, we sincerely appreciate your support!

Links

License

  • Hardware: CC-BY-SA
  • Firmware: CC-BY-SA
  • Bootloader: GPL