Logic Analyzer core: Trigger Sums

From DP

Jump to: navigation , search

The trigger summing logic combines the results of the trigger terms, range detectors, edge detectors and timers. OLS-documentation-TrigSum.png

Figure 19 - Combination Trigger Sum

Each of the operations (the "OR" blocks shown above) are implemented using LUT memories. Therefore, they can be configured with any logical operation. Typical functions are: AND, NAND, OR, NOR, XOR, NXOR, A-only, B-only, ANY, or NOP.

In addition, the LUT memories can be used to invert the result of a trigger term, range, edge or timer detect (anything in the first column above). For example, allowing "a" or "not a", or "in_range" or "out of range" variations, etc...

There are three trigger sums per sequencer state, and sixteen trigger sequencer states, for a total of 48 trigger sums which need configuring.


Contents

7.1 Trigger Sum Inputs

As mentioned earlier, the inputs to the sum are trigger terms, range detectors, edge detectors and timers. Results of all inputs feed into the "pair" LUT's (which evaluate a pair of sum inputs each).

  • Trigger Terms. 32-bit masked compares. Each term supplies a two bit result. LSB corresponds to indata[15:0]. MSB to indata[31:16]. Both bits must be asserted to indicate a hit.
  • Range Detectors. The range detectors similarly supply two signals. LSB is the lower limit hit. MSB is upper limit hit. Both bits must be asserted to indicate a hit.
  • Edge Detectors. Single hit/miss signal. Fed into both bits 2 & 3 of pair LUT.
  • Timer. Single hit/miss signal. Fed into both bits 2 & 3 of pair LUT.


7.2 Trigger Sum Operations

Operation codes for the "pair" LUT's are a little confusing since terms & range detector supply two signals each (both of which must be asserted for a hit).

Sum Inputs    AND    NAND    OR    NOR    XOR    NXOR    A    B
0    0    0    0    0    1    0    1    0    1    0    0
0    0    0    1    0    1    0    1    0    1    0    0
0    0    1    0    0    1    0    1    0    1    0    0
0    0    1    1    0    1    1    0    1    0    1    0
0    1    0    0    0    1    0    1    0    1    0    0
0    1    0    1    0    1    0    1    0    1    0    0
0    1    1    0    0    1    0    1    0    1    0    0
0    1    1    1    0    1    1    0    1    0    1    0
1    0    0    0    0    1    0    1    0    1    0    0
1    0    0    1    0    1    0    1    0    1    0    0
1    0    1    0    0    1    0    1    0    1    0    0
1    0    1    1    0    1    1    0    1    0    1    0
1    1    0    0    0    1    1    0    1    0    0    1
1    1    0    1    0    1    1    0    1    0    0    1
1    1    1    0    0    1    1    0    1    0    0    1
1    1    1    1    1    0    1    0    0    1    1    1

Figure 20 - Pair LUT Operations


The mid LUT is straight forward. A pure 4-input logic gate:

Sum Inputs    AND    NAND    OR    NOR    XOR    NXOR
0    0    0    0    0    1    0    1    0    1
0    0    0    1    0    1    1    0    1    0
0    0    1    0    0    1    1    0    1    0
0    0    1    1    0    1    1    0    0    1
0    1    0    0    0    1    1    0    1    0
0    1    0    1    0    1    1    0    0    1
0    1    1    0    0    1    1    0    0    1
0    1    1    1    0    1    1    0    0    1
1    0    0    0    0    1    1    0    1    0
1    0    0    1    0    1    1    0    0    1
1    0    1    0    0    1    1    0    0    1
1    0    1    1    0    1    1    0    0    1
1    1    0    0    0    1    1    0    0    1
1    1    0    1    0    1    1    0    0    1
1    1    1    0    0    1    1    0    0    1
1    1    1    1    1    0    1    0    0    1

Figure 21 - Mid LUT Operations


The final LUT only has two inputs. It's configured as a 2-input logic gate:

Sum Inputs    AND    NAND    OR    NOR    XOR    NXOR
0    0    0    0    0    1    0    1    0    1
0    0    0    1    0    1    1    0    1    0
0    0    1    0    0    1    1    0    1    0
0    0    1    1    1    1    1    0    0    1
0    1    0    0    0    0    0    0    0    0
0    1    0    1    0    0    0    0    0    0
0    1    1    0    0    0    0    0    0    0
0    1    1    1    0    0    0    0    0    0
1    0    0    0    0    0    0    0    0    0
1    0    0    1    0    0    0    0    0    0
1    0    1    0    0    0    0    0    0    0
1    0    1    1    0    0    0    0    0    0
1    1    0    0    0    0    0    0    0    0
1    1    0    1    0    0    0    0    0    0
1    1    1    0    0    0    0    0    0    0
1    1    1    1    0    0    0    0    0    0

Figure 22 - Final LUT Operations


All LUT's can also be programmed to NOP (ie: always output zero), or ANY (always output one), or anything else you can think up.

7.3 Example (Trigger Sum Initialization)

#define OP_NOP 0
#define OP_ANY 1
#define OP_AND 2
#define OP_NAND 3
#define OP_OR 4
#define OP_NOR 5
#define OP_XOR 6
#define OP_NXOR 7
#define OP_A 8
#define OP_B 9
 
//                    NOP    ANY    AND    NAND   OR     NOR    XOR    NXOR   A      B
int pairvalue[] =  {0x0000,0xFFFF,0x8000,0x7FFF,0xF888,0x0777,0x7888,0x8777,0x8888,0xF000};
int midvalue[] =   {0x0000,0xFFFF,0x8000,0x7FFF,0xFFFE,0x0001,0x0116,0xFEE9,0xEEEE,0xFFF0};
int finalvalue[] = {0x0000,0xFFFF,0x0008,0x0007,0x000E,0x0001,0x0006,0x0009,0x0002,0x0004};
 
void write_trigger_sum (
  int statenum, int stateterm,
  int op_ab, int op_c_range1, int op_d_edge1, int op_e_timer1,
  int op_fg, int op_h_range2, int op_i_edge2, int op_j_timer2,
  int op_mid1, int op_mid2, int op_final)
{
  write_select (0x40 + (statenum*4) + stateterm);
  write_chain (finalvalue[op_final]);
  write_chain ((midvalue[op_mid2]<<16) | midvalue[op_mid1]);
  write_chain ((pairvalue[op_j_timer2]<<16) | pairvalue[op_i_edge2]);
  write_chain ((pairvalue[op_h_range2]<<16) | pairvalue[op_fg]);
  write_chain ((pairvalue[op_e_timer1]<<16) | pairvalue[op_d_edge1]);
  write_chain ((pairvalue[op_c_range1]<<16) | pairvalue[op_ab]);
}

Figure 23 - Initialize Trigger Sum

License note

This document is Copyright © 2011 Ian Davis
Released under the  GNU General Public License