Logic Analyzer core: Trigger Sequence States
From DP
Sequence states allow you to control how the analyzer evaluates and stores sampled data. Each state gives you control over data capturing, searching for a target (optionally multiple times), or branching to another sequence should a special condition occur. On a hit, the analyzer advances to the next sequence state. It can also trigger the analyzer controller & start/stop timers. With 16 sequence states, you can create complex protocol following triggers.
Figure 24 - Example Sequence Level
For each state you specify:
- Capture Term (sum of trigger terms, range checks, edge detect & timer hits)
- Hit Term (sum of trigger terms, range checks, edge detect & timer hits)
- Else Term (sum of trigger terms, range checks, edge detect & timer hits)
- Occurrence Count
- Else State
- Timer Control Flags (start/stop/clear for timers 1 & 2)
- Trigger Flag
The trigger sequencer itself is a relatively simple state machine. Pseudocode for it is:
if (sampled_input valid) then { if (capture_term valid) then capture data if (hit_term valid) then { increment hit_count if (hit_count == fsm_occurence_count) then { update_timers reset hit_count if (fsm_trigger || last_state) then assert run to controller if (!last_state && !fsm_last_state) advance to next state } } otherwise if (else_term valid) then { reset hit_count go to state "fsm_else_level" } }
Figure 25 - Trigger Sequencer State Machine
8.1 Example (Trigger Sequence Initialization)
#define TRIGSTATE_STATENUM_MASK 0xF #define TRIGSTATE_OBTAIN_MASK 0x000FFFFF #define TRIGSTATE_ELSE_BITOFS 20 #define TRIGSTATE_STOP_TIMER0 0x01000000 #define TRIGSTATE_STOP_TIMER1 0x02000000 #define TRIGSTATE_CLEAR_TIMER0 0x04000000 #define TRIGSTATE_CLEAR_TIMER1 0x08000000 #define TRIGSTATE_START_TIMER0 0x10000000 #define TRIGSTATE_START_TIMER1 0x20000000 #define TRIGSTATE_TRIGGER_FLAG 0x40000000 #define TRIGSTATE_LASTSTATE 0x80000000 void write_trigger_state ( int statenum, // 0 to 15 int last_state, int set_trigger, int start_timer, // bit0=timer1, bit1=timer2 int stop_timer, // bit0=timer1, bit1=timer2 int clear_timer, // bit0=timer1, bit1=timer2 int else_state, // 0 to 15 int obtain_count) { write_select (statenum & TRIGSTATE_STATENUM_MASK); unsigned int value = ((else_state & TRIGSTATE_STATENUM_MASK)<<TRIGSTATE_ELSE_BITOFS) | (obtain_count & TRIGSTATE_OBTAIN_MASK); if (last_state) value |= TRIGGER_LASTSTATE; if (set_trigger) value |= TRIGSTATE_TRIGGER_FLAG; if (start_timer & 1) value |= TRIGSTATE_START_TIMER0; if (start_timer & 2) value |= TRIGSTATE_START_TIMER1; if (stop_timer & 1) value |= TRIGSTATE_STOP_TIMER0; if (stop_timer & 2) value |= TRIGSTATE_STOP_TIMER1; if (clear_timer & 1) value |= TRIGSTATE_CLEAR_TIMER0; if (clear_timer & 2) value |= TRIGSTATE_CLEAR_TIMER1; write_chain (value); }
Figure 26 - Initialize Trigger Sequence
License note
This document is Copyright © 2011 Ian Davis Released under the GNU General Public License