Logic Analyzer core: Timers
From DP
Timer limits are very simple. You write a 36 bit value. Lower 32 bits to trigger register 0x38/0x3A. Upper 4 bits to trigger register 0x39/0x3B. The fpga reference clock is 100Mhz, so each timer tick corresponds to 10ns.
Figure 17 - Timer
The 36-bit timers have a range from 10ns to 687 seconds (over 11 minutes). Timers are started, stopped, and cleared under control of the trigger sequencer.
6.1 Example (Timer Initialization)
void write_trigger_limit (int timersel, uint64_t value) { write_select (0x38 + (timersel&1)*2); write_chain (value & 0xFFFFFFFF); write_select (0x39 + (timersel&1)*2); write_chain (value>>32); }
Figure 18 - Initialize Timer Values
License note
This document is Copyright © 2011 Ian Davis Released under the GNU General Public License