Logic Analyzer core: Introduction
The Open Logic Sniffer Demon Core FPGA offers many of the features found in an HP 16500 / 16550 timing logic analyzer. Combined with the OLS's small size it yields a very potent little tool.
- SUMP logic analyzer client compatible.
- 16 pin buffered probe header (5V tolerant)
- 16 pin unbuffered (wing) header3.3V tolerant)
- 24K samples (8 bit captures)
- Maximum 200Mhz sample rate(using demux mode)
- USB interface, USB powered, & USB upgradeable.
- Basic/Legacy trigger with four level parallel or serial target matching
- Advanced trigger with 16 sequence states, 10 pattern matches, two range checkers, two edge detectors & two timers (10ns resolution, 600 second range).
- RLE compression of captures.
Figure 1 - Block Diagram
1.1 Advanced Trigger
The advanced trigger offers many features found in an HP16500 / 16550 timing logic analyzer. It offers 16 sequence levels with two way branching (a programmable state machine), ten pattern value comparisons, two range checks, two edge checks, and two counter/timers.
There are several different modules within the advanced trigger, each needing its own spin on configuration. These are:
- Trigger Terms. Terms perform the actual bitwise masked pattern comparisons on the 32-bit incoming data. There are ten terms. Each one needs 128 bits of configuration data.
- Trigger Range Detectors. The two range detectors look for values falling between a lower & upper 32-bit limit. Each range check uses two 32-bit magnitude comparisons., one for the upper compare, one for the lower. A match means: “upper >= indata >= lower”. Each range detector needs 512 bits of configuration data.
- Trigger Edge Detectors. The two edge detectors compare sampled input against a delayed version. Rising edges, falling edges, or both, or neither can thus be detected. Each needs 256 bits of configuration data.
- Trigger Timers. Timers are started/stopped under control of the trigger sequence states. There are two timers, each needing a 36 bit limit value. The timers have a range from 10ns to over 11 minutes.
- Trigger Sums. These combine the results of the trigger terms, range comparisons, edge checks, and timer checks. There are 11 logic units programmable to perform any logic function. Examples are AND/NAND/OR/NOR/XOR/NXOR. The logic units are combined in a tree structure, and combine/sum all trigger sources down to a match/miss signal. There are three trigger sums per trigger state, and 16 trigger states, totaling 48 sums. Each sum needs 192 bits of configuration data.
- Trigger Sequence States. Each state is guided by the results of three trigger sums (see above). If the “hit” trigger sum matches, for a specified number of occurrences, the FSM advances. A hit also controls if a timer is started/stopped/cleared. If the “else” trigger sum matches, the FSM branches to the “else” state. Data capture is controlled by the “capture” trigger sum – if it matches, a sample is taken. If not, then not. Each state takes 32 bits of configuration.
Each module will be described in detail in the following chapters.
This document is Copyright © 2011 Ian Davis Released under the GNU General Public License