# Logic Analyzer core: Edge Detectors

The edge detectors compare a delayed sample to the current one. If any bit changes, with a rising edge, falling edge, either rising or falling edge, or neither (no change), it can be detected.

Each 4-input logic block evaluates two bits of input, and two bits of delayed input.

Figure 15 - Edge Detector LUT

All that is left now is placing 1's in the LUT where the edges of interest occur. Since two bits are evaluated in parallel, this becomes slightly more complex.

The following truth table shows the possible combinations.

```DLY
INDATA1 DLY
INDATA0 INDATA1 INDATA0  RISE0  FALL0  RISE1  FALL1  BOTH0  BOTH1  NONE0  NONE1
0        0      0       0       0      0      0      0      0      0      1      1
0        0      0       1       1      0      0      0      1      0      0      1
0        0      1       0       0      0      1      0      0      1      1      0
0        0      1       1       1      0      1      0      1      1      0      0
0        1      0       0       0      1      0      0      1      0      0      1
0        1      0       1       0      0      0      0      0      0      1      1
0        1      1       0       0      1      1      0      1      1      0      0
0        1      1       1       0      0      1      0      0      1      1      0
1        0      0       0       0      0      0      1      0      1      1      0
1        0      0       1       1      0      0      1      1      1      0      0
1        0      1       0       0      0      0      0      0      0      1      1
1        0      1       1       1      0      0      0      1      0      0      1
1        1      0       0       0      1      0      1      1      1      0      0
1        1      0       1       0      0      0      1      0      1      1      0
1        1      1       0       0      1      0      0      1      0      0      1
1        1      1       1       0      0      0      0      0      0      1      1```

Rising edges are detected when DLY_INDATA is zero, and INDATA is one. Falling edges when DLY_INDATA is one, and INDATA is zero. Both edges are detected by simply combining columns. Neither edge is detected by inverting the "both" column.

## 5.1 Example (Edge Detector Initialization)

```#define EDGE_RISE0 0x0A0A
#define EDGE_RISE1 0x00CC
#define EDGE_FALL0 0x5050
#define EDGE_FALL1 0x3300
#define EDGE_BOTH0 (EDGE_RISE0|EDGE_FALL0)
#define EDGE_BOTH1 (EDGE_RISE1|EDGE_FALL1)
#define EDGE_NEITHER0 (~EDGE_BOTH0 & 0xFFFF)
#define EDGE_NEITHER1 (~EDGE_BOTH1 & 0xFFFF)

void write_edge (int edgesel,
unsigned int rising_edge, unsigned int falling_edge, unsigned int neither_edge)
{
write_select (0x34 + (edgesel&1));

unsigned int lutvalue=0;
for (int i=0; i<16; i=i+1) {
// Evaluate indata bit1...
lutvalue |= EDGE_NEITHER1;
else {
if (rising_edge & bitmask) lutvalue |= EDGE_RISE1;
if (falling_edge & bitmask) lutvalue |= EDGE_FALL1;
}

// Evaluate indata bit0...
lutvalue |= EDGE_NEITHER0;
else {
if (rising_edge & bitmask) lutvalue |= EDGE_RISE0;
if (falling_edge & bitmask) lutvalue |= EDGE_FALL0;
}

if ((i&1)==0)
lutvalue <<= 16;
else {
write_chain (lutvalue); // write total of 256 bits
lutvalue = 0;
}
}
}```

Figure 16 - Initialize Edge Detector LUT Values

```This document is Copyright © 2011 Ian Davis