Lattice ispMACH 4000 CPLD quick start

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Contents

Features

  • Different voltage versions make a single supply system possible
  • 5volt tolerant IO pins
  • Unlike most FPGA, CPLDs are static and store their configuration permanently.
  • This chip uses CMOS EEPROM and is reprogrammable at least 1000 times
  • Pull-up/pull-down resistors, bus keepers
  • Several devices in easy-to-solder TQFP-44 packages
  • Available at Mouser, among others, starting at $2

Resources

  • [ Lattice ispMACH 4000 homepage]
  • [ Lattice ispMACH 4000 family features]
  • [ Lattice ispMACH 4000 family datasheet]
  • CPLD development tutorials

Development and programming

Lattice has a free CPLD development package called ispLEVER Classic. There seem to be newer Lattice compilers, but they don't support the ispMACH 4000 in the free version.

JTAG cables

Loaders

Basic circuit

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Power

Requires, at minimum, a 3.3volt supply.

  • 3.3volts (4000V), 2.5volts (4000B) or 1.8volts (4000C/Z) - core supply (VCCINT)
  • 1.8volts, 2.5volts, or 3.3volts - IO supply for the IO pins, use your preferred interface voltage (VCCIO)

JTAG programming connections

6x1 JTAG pinout
Pin SignalDirection
1 V+
2 GND
3TCKInput
4TDOInput
5TDIOutput
6TMSInput

Common JTAG pinout.

Clock source

A clock source is only required if your design needs it. If you plan to use a clock, connect it to a GCLK pin for best results.

  • GCLK pins are optimized to distribute a clock signal to all macrocells with minimum skew and resources. If you plan to use a clock with the CPLD, connect it to one of these pins if possible. The GCLK features must be applied in the CPLD design or the GCLK pin will be an ordinary IO pin.

Peripherals

IO

Resources