# CPLD intro 4: replacing simple logic vhdl

### From DP

## Contents |

## Overview

CPLDs are traditional used to replace (lots) of basic logic

## VHDL

There are several options to describe the logic one wants to replace and VHDL is one of them. We try to provide a small tutorial here, but see the link section for a more extensive tutorial.

A (simple) vhdl file has these parts:

### Includes

library ieee; use ieee.std_logic_1164.all;

All VHDL code use these libraries. They provide a declaration for standard input, output and in/output pins.

### In/outputs

We declare 'the logic' (AND_2) and describe the in and outputs:

entity AND_2 is port( in1: in std_logic; in2: in std_logic; out1: out std_logic ); end AND_2;

It will be used to replace a simple AND port with two inputs and one output.

### logic description

architecture logicdesc of AND_2 is begin out1 <= in1 and in2; end logicdesc;

This describe how the interaction is between the inputs and outputs.

## Example AND (complete)

library ieee; use ieee.std_logic_1164.all; entity AND_2 is port( in1: in std_logic; in2: in std_logic; out1: out std_logic ); end AND_2; architecture logicdesc of AND_2 is begin out1 <= in1 and in2; end logicdesc;

## Example truthtable

Same only implemented by a truthtable:

library ieee; use ieee.std_logic_1164.all; entity AND_2 is port( in1: in std_logic; in2: in std_logic; out1: out std_logic ); end AND_2; architecture logicdesc of AND_2 is begin process(x, y) begin if ((x='1') and (y='1')) then F <= '1'; else F <= '0'; end if; end process; end logicdesc;

## Resources on the web

[1] VHDL code

[2] VHDL tutorial