CPLD intro 1: Light a LED

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Contents

Overview

This is a very simple tutorial to walk you through your first CPLD design and introduce the ISE Webpack tools.

We only have one goal for this demo: light a LED on the development board. Open the ISE project CPLDIntro1LEDon in the XC9572XL or XC2C64A folder.

Tutorial 1 truth table
LED D1
ON

Schematic

Cpld-tutorial-external-circuit.png

The XC2C64A and XC9572XL development boards have two LEDs and a push button. We'll light LED D1 in this demo.

CPLD dev board connections
IO pin connection
LED D1 P39
LED D2 P38
Button BP P18

To turn on the LED we need to connect pin 39 (P39) to the power supply inside the CPLD.

Cpld-intro1.png

We do this with a simple schematic entry, just like designing a circuit board in Eagle. If you've used a circuit design app before the interface should be fairly self-explanatory, but you can see how we constructed this schematic step-by-step below.

  • VCC is a schematic element that represents a connection to the CPLD power supply
  • OBUF is an output buffer that takes an internal CPLD signal and connects to a pin. All inputs and outputs from the CPLD must be attached to a buffer element
  • LED is an output marker. Output and input markers will be assigned to CPLD pin numbers in the UCF file below

Assign pin numbers in UCF

#PIN MAP OF DANGEROUSPROTOTYPES.COM CPLD BREAKOUT BOARDS
#LICENSE: CC-0 (CREATIVE COMMONS 0)
NET "LED"            LOC =  "P39";

Input and output markers in the schematic are mapped to actual CPLD pin numbers in the UCF file. This is an example UCF file that defines the LED connection on the development boards.

  • The Pxx numbers are the actual pin number on the CPLD. Set the LOC (location) of the LED marker to P39. Easy.
  • ISE has a GUI utility to assign pin numbers, but it doesn't work with CoolRunner-II CPLDs.

We mapped the LED output marker to pin 39, which is attached to LED D1 on the development boards.

Synthesize the design

Cpld-intro-synthesize.png

Synthesizing is the CPLD and FPGA equivilent of compiling. It turns your schematic or VHDL/Verilog code into a bitstream that implements the design.

When your schematic is ready push the green play button to synthesize the design. ISE will report any errors and generate a bitstream.

  • It will take a while, up to a few minutes
  • A synthesis report will show how many of the CPLD resources are used

Export a JTAG programming file

Cpld-itutorial-ise-impact.png

Most CPLDs are programmed through a 4-wire JTAG interface. ISE programs CPLDs via the IMPACT utility, listed on the design panel as shown.

Only parallel cables and Xilinx USB cables can be used directly from IMPACT. We can also export generic JTAG programming files called (X)SVF. These files can be loaded with an external (X)SVF player utility and output through any JTAG programmer such as the Bus Pirate or Bus Blaster.

Program the CPLD

With (X)SVF programming files in hand we're ready to program the CPLD.

Just about any JTAG programmer with an (X)SVF player can now be used to program the CPLD. Here's some examples with our own programmers:

Making the schematic

This is a detailed look at the ISE features we used to create the schematic.

We think the schematic editor is annoying, but it is also pretty intuitive. Instead of boring you with all this stuff up top, we jumped into the action. If you want to see the details, here they are.

New schematic project

Cpld-sch-tut-1.png

  • Create a new schematic project with the File->New Project dialog, select your CPLD type and package

Add symbols

Cpld-ise-symbolds-tab.png

  • With the new blank schematic open, click on the Symbols tab at the bottom of the menu on the left of the screen
  • The available schematic symbols are shown by category
  • Clock on a symbol to place it on the schematic

Connect stuff

Cpld-tutorial-ise-wiretool.png

  • Use the wire tool (looks like a pen) to connect schematic symbols

Add IO markers

Cpld-tutorial-ise-iomarker.png

  • IO markers indicate where signals enter or exit the schematic
  • External input or outputs should always connect to a buffer symbol before entering other logic
  • Click the IO marker button on the schematic toolbar (highlighted in the image above)
  • Choose input, output, or bidirectional type
  • Click on the end of wires and symbols to add IO markers

Name IO markers

Cpld-ise-sch-net-1.png

  • The IO marker name is used in the UCF file to assign actual CPLD pins to the schematic
  • To change the IO name: right click the IO and choose Rename port

Cpld-ise-sch-net-2.png

  • Change the IO marker name in the dialog box and hit ok
  • This output is now named LED

Assign pins

#PIN MAP OF DANGEROUSPROTOTYPES.COM CPLD BREAKOUT BOARDS
#LICENSE: CC-0 (CREATIVE COMMONS 0)
NET "LED"            LOC =  "P39";

Input and output markers in the schematic are mapped to actual CPLD pin numbers in the UCF file.

  • The Pxx numbers are the actual pin number on the CPLD
  • We set the LOC (location) of the LED marker to P39, which is attached to LED D1 on the development boards