CPLD: simulate designs

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After a successful 'build' a simulation of the design is possible.

Start simulation

Simulate1.jpg

Change the view from 'implementation' to 'Simulation' and doubleclick 'Simulate Behavioral Modal'. We used the tutorial 4 files for the simulation.

Simulate2.jpg

Setup clock signal

Simulate3.jpg

And a 'Force clock' to both inputssignals.

  • Right-click on 'Value' and select 'Force clock'
  • We add a squarewave with a period of 100ms to in1 and a squarewave with a period of 200ms to in2.

Run simulation

Simulate4.jpg

Select the 'run-all' option.

Simulate5.jpg

By zooming in a simular simulation is visible.