Bus Blaster v1 manufacturing resources

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Contents

Manufacturing prototype verification

Setup

Download and install the drivers:

Download and install urJTAG:

Connections

Bbv1-proto-test.jpg

We will chain scan the FPGA on the Logic Sniffer to verify the Bus Blaster functionality. You can use any simple FPGA, CPLD, or ARM development board for the test instead.

test connections
Bus Blaster JTAG Logic Sniffer JTAG
VTG 2V5
GND GND
TCK TCK
TDO TDO
TDI TDI
TMS TMS
  1. Connect the Bus Blaster to the Logic Sniffer as shown in the table
  2. Plug in the Bus Blaster USB
  3. Plug in the Logic Sniffer USB, LED2 (TARGET PRESENT) should light

Function test

Urjtag-bbv1-test-full.png

  • Start urJTAG
jtag> cable jtagkey
  • Setup the Bus Blaster interface with "cable jtagkey"
jtag> detect
  • Perform the chain scan with "detect"
  • urJTAG detects a Xilinx device, manufacturer unknown

Errors

jtag> detect
Warning: TDO seems to be stuck at 1

If the chip is not detected:

  • Check the JTAG connection
  • Make sure there are no other FTDI chips attached to the PC (urJTAG might attach to wrong programmer)