Altera MAX 3000A/7000A CPLD quick start

From DP

Jump to: navigation , search

Contents

Features

  • 2.5volt or 3.3volt IO, 3.3volt core supply required
  • 5volt tolerant IO pins
  • Comparable to Xilinx XC9500XL, but higher speeds available
  • Unlike most FPGA, CPLDs are static and store their configuration permanently.
  • This chip uses CMOS EEPROM and is reprogrammable about 100 times
  • Several devices in easy-to-solder TQFP-44 packages
  • Available at Digikey, among others, starting at $1

3000A vs 7000A

Very similar chips. Pinout is almost the same, but MAX7000A has fewer ground pins.

  • 3000A is cheapest

Resources

Development and programming

Altera has a free FPGA and CPLD development package called Quartus II Web Edition. This is the only development tool we're aware of.

JTAG cables

Uses a standard JTAG programming interface or can also use a proprietary programming method

  • Master/Byte/Bit Blaster cables and Quartus
  • Quartus outputs JAM/STAPL programming files. STAPL support is being added to urJTAG, then it should be possible to program with a FT2232 JTAG programmer (like the Bus Blaster)

Loaders

Load configurations into the CPLD or FPGA by running a JAM/STAPL encoded file exported from Quartus.

  • UrJTAG - STAPL support is being added to urJTAG, then it should be possible to program with a FT2232 JTAG programmer (like the Bus Blaster)
  • OpenOCD - detects FPGA/CPLDs, but doesn't do much with them

Basic circuit

480px

Power

Requires, at minimum, a 3.3volt supply.

  • 3.3volts - core supply and JTAG pins (VCCINT)
  • 2.5volts or 3.3volts - IO supply for the IO pins, use your preferred interface voltage (VCCIO)

JTAG programming connections

6x1 JTAG pinout
Pin SignalDirection
1 V+
2 GND
3TCKInput
4TDOInput
5TDIOutput
6TMSInput

Common JTAG pinout.

Clock source

A clock source is only required if your design needs it. If you plan to use a clock, connect it to a GCLK pin for best results.

  • GCLK pins are optimized to distribute a clock signal to all macrocells with minimum skew and resources. If you plan to use a clock with the CPLD, connect it to one of these pins if possible. The GCLK features must be applied in the CPLD design or the GCLK pin will be an ordinary IO pin.

Peripherals

IO

There are also some pins with special features, though they are not used unless specifically enabled in the CPLD synthesis:

  • GCLK (global clock) - optimized to distribute a clock signal to all macrocells with minimum skew and extra resources
  • GCLR (global clear) - optimized path to the Set/Reset signal of all macrocells, allows synchronous reset of the flip-flop in all cells with minimum extra resources
  • OE (output enable) - optimized to put all CPLD pins in a high impedance state

Resources