Workshop video #03: Bus Blaster JTAG debugger history

In this video Texas Instruments gets the Big Box award, and we discuss the evolution of the Bus Blaster JTAG debugger.

The Bus Blaster is our inexpensive, open source JTAG debugger based on the FTDI FT2232H UBS->serial chip. This chip has 2 JTAG interfaces and can program/debug two separate JTAG targets.

  • Bus Blaster v1 used 5 discrete logic chips to do level translation between the FT2232 JTAG debugger chip at 3.3volts and the target chip at 1.2-3.3volts.
  • v2/v2.5 replaced the expensive logic chips with a reprogrammable CPLD. We connected the unused secondary JTAG port on the FT2232 to the CPLD programming port. The buffer can be programed over USB without any extra hardware.
  • v3 is a minor update of v2.5, fit for a case. We incremented to v3 because there is a slightly different connection between the FT2232 and CPLD. We moved the FT2232 synchronous clock output pin to a global clock pin on the CPLD. v2 and v3 bitstreams will not be compatible.
  • Bus Blaster v4 adds a switch to toggle the secondary JTAG pins between the programming the buffer, and connecting to the external target. Bus Blaster v2/v3 supports most features of the new SWD reduced-wire JTAG interface. One feature, SVO, requires the UART hardware in the secondary JTAG port we use to program the buffer CPLD.  Quick fix: add a switch. A larger CPLD is used because we now need to connect all the extra pins of the secondary JTAG port to the CPLD.

There is absolutely no estimated date of production for the new boards. v2.5 will probably be the only Bus Blaster available for the next year.

Get a Bus Blaster v2 for $34.95.

Pinnacle Studio 15 video editing software refused to render the whole video, this first part is what we could get. Pinnacle also has a 5x max speedup, so the soldering time-lapse was nearly 20 minutes. The second part, PCB assembly, will go up tomorrow using a new video editing craplication…

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15 Comments

  1. TI India changed the contest rules after they got the heat. They let us know with a comment. Sth good finally. BTW I had the same big box thing with my development kit from TI, I received 2 boxes, one for the dev kit, other for the JTAG debugger.

  2. Hi,
    Great to see the BusBlaster development. Another handy tool like BusPirate.
    However I would wait till it matures. Till then BusPirate would be the handy companion.

    Thanks Ian for the video

  3. On the Bus Blaster v4, instead of using discrete ICs to switch the FT2232’s second port between the 100-pin CPLD’s config and I/O pins, you could use a cheap CPLD to do the switching.

    But then you’d need to program the cheap CPLD. So just add a second cheap CPLD to switch between config and I/O pins on the first cheap CPLD.

    But then you’d need to program the second cheap CPLD. So just add a third cheap CPLD to switch between config and I/O pins on the second cheap CPLD.

    But then you’d need to program the Nth cheap CPLD. So just add a (N+1)th cheap CPLD to switch between config and I/O pins on the Nth cheap CPLD.

  4. Ian:

    I think you coined a new phrase for Webster or the urban dictionary , “craplication…” LOL

  5. Small point but still worth pointing out is that SWD (serial wire debug) is not JTAG. It is a debug and trace interface designed by ARM, and lacks all the in-circuit testing facilities that were the whole reason JTAG was invented. The only relation between the two is that many ARM parts include both interfaces, multiplexed onto the same pins.

    Does the Bus Blaster v4 support trace port pins, or only the basic two-pin interface?

    1. Thanks for the clarification. Bus Blaster v2/3 supports the SWD features. Bus Blaster v4 supports SWD and SWV. (Serial Wire Viewer).

  6. i was not really paying close enough attention when Ian gave out the biggest box award, i almost spit out a mouthful of coffee.lol

    1. I geddit ( skybeaver, box award) but just wanted to say about packaging boxes, back in May 2008 I sampled a couple of the SI570 chips, the box was about the same size. Inside was four smaller boxes and lots of packaging material (air pillows). Two of the boxes were labelled as “Empty Box” I kid you not!

      About 6 Si570 should occupy the volume the size of a 40pin DIP chip.

    1. Nothing really, the v4 is vaporware, a dream, just an idea. If you can wait 1 or 2 or 3years for a JTAG debugger, then I guess it makes sense to wait for v4.

  7. Thanks Ian for the clarification.

    I guess I’ll just have to wait for v4 then :)

    But, seriously, how soon can I get my hands on the v2.5 in the mean time; while I wait for the vaporware ?

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