## Dangerous DSO part 5: Testing and conclusions

Posted on Friday, May 13th, 2011 in Development, FPGA, oscilloscope, Prototypes by Ian

It’s the last day of our week-long Dangerous DSO adventure. Yesterday we simulated the analog front-end and found a few changes to test. First, we’re going to increase the ADC buffer gain to 2. That should make vertical offset adjustment easier. Second, we’re going to try a more refined input range divider with a 900K fixed resistor and 100K trimmer resistor. For background on the front-end see the previous articles.

We hope you enjoyed this series, we had a blast designing the hardware and writing about it. Dangerous DSO v1 PCBs are in the free PCB drawer, if you are serious about building this board please let us know via the contact form. The Dangerous DSO source download includes the v1 design files, the current v1a update, and LTspice simulation files. Now on to the final day of testing!

A big thank you to everyone who helped realize this project. It would not have been possible without you.

Dangerous DSO is a new logic analyzer/oscilloscope design we’ve been using in the lab. This is not a finished project, it will not be produced. We’re posting our current progress to get some feedback. Don’t miss Part 1: There’s so much between 0 and 1, Part 2: Feed and water your ADC, Part 3: Messing with the front end, and Part 4: Over simulated.

Baseline

This capture was done with the original circuit and an op-amp gain of 1.667.

Set gain to 2

Our LTspice simulations showed that it’s easier to get a 2volt offset for the ADC when the op-amp gain is 2. The original Bitscope ADC buffer has a gain of 1.667.

• Vout=(1+R33/R34)*Vin.
• To solve for gain set Vin=1 and enter the resistor values
• Gain=(1+(220/220))=2

Gain is determined by R33 and R34. To set the gain at 2 we replaced the 330ohm op-amp feedback resistor with 220ohm. This forms a 1:2 divider between the inverting input and the the op-amp output. Now the output to responds double to changes of input.

Here’s a capture with an op-amp gain of 2. The extra gain made the input adjustment really difficult. We couldn’t calibrate it as well as before.

The transitions seem to over/undershoot a lot. We guess this is op-amp noise and not part of the actual signal. This looks too messy to believe it’s representative of the PIC PWM output.

Mod input divider for better control

Double gain means we need to divide a +/-10volt input signal by 40 before feeding it to the op-amp.

• 0.975M+0.025M=/40=+/- 10volt input
• 0.950M+0.050M=/20=+/- 5volt input
• 0.900M+0.100M=/10=+/- 2.5volt input

Most usable input ranges are in the bottom 100K ohms of the trimmer. A single-turn trimmer resistor give us about 5degrees of usable adjustment room, that makes calibration a pain.

We removed the 1M trimmer and replaced it with a 100K trimmer. The extra 900K ohms comes from a fixed value resistor. We didn’t have a 100K SMD trimmer, so this test was done with a breadboard and through-hole parts.

Here’s a capture with an op-amp gain of 2 and the modified input divider.  The input range was a lot easier to adjust, definitely a worthwhile update to the next revision. Noise and garbage from using a breadboard and fly-wires is obvious.

Calibration

Between each circuit update we recalibrate the center offset and input divider. This is the basic procedure:

1. Connect the oscilloscope input to ground
2. Run a capture
3. Adjust the offset with R8 a little each time and do another capture
4. Repeat step 3 until the oscope line is in the middle of the graph
5. Once centered, remove the ground connection
6. Connect the input to a 50kHz square wave from the Bus Pirate (command g, then both default values)
7. Perform captures and adjust the input divider with R12 until the signal fits in the limits of the display

Conclusions

Things don’t look great for the double gain setup. Additional gain seems to magnify noise, moving back to 1.667 would probably be best. After Maker Faire we’ll post a few comparisons against an actual o-scope.

This entry was posted on Friday, May 13th, 2011 at 10:00 am and is filed under Development, FPGA, oscilloscope, Prototypes. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

### 17 Responses to “Dangerous DSO part 5: Testing and conclusions”

1. Jason Olshefsky says:

I’m surprised if this isn’t already the design, but to trim a 10:1 voltage divider, wire a 920K resistor in series with a 5K pot, then 100K to ground. R[total] is 1025K so 1/10 of that is 102.5K — right in the middle of the 5K pot. If the resistors have perfect values the ratio trim adjustment is 10.25:1 to 9.76:1 which makes it a lot easier to trim.

2. bearmos says:

Is it convenient to share an approximate total BOM cost for this? I saw the BOM in the wiki, but no cost.

• Ian says:

I just used stock parts, scraps, and samples. Nothing was too expensive except the FPGA, which is 12 or 14 bucks. I guess the ADC would be \$5+ in small quantities, and the op-amp \$2.50

3. bearmos says:

So probably around \$30 after the random passives are included? Very cool, nice work.

4. rik says:

where do you store stuff, you cant send 50MSPS of data every sec trough USB so you gotta have a buffer somewhere.
do you store all the stuff in the FPGA and so yes, how much RAM do you use for the analog part?

• Ian says:

Yes, samples are stored in RAM. It is divided among the channels. 16LA + DSO = 8K max, 8LA+DSO=12K max, DSO only is 24K max.

5. bearmos says:

So at max sample rate, DSO only will acquire up to 24k samp/50 MSPS = 480 uS worth of time series, correct?

• Ian says:

That seems right. Not very long sampling.

• bearmos says:

Well, total time isn’t, but that’s just because it’s sampling so quickly (obviously). As a comparison, an Agilent 54825 (new was around \$19k) samples at 2GS/s and up to 32K samples, for a grand total of 16 uS capture. The key is to be able to dial down the sample rate for the slower signals and to have trigger options so you start the capture when you need to.

The cool part about having a combined DSO and LA on the same FPGA is that you can easily use the digital signals as triggers for your analog acquisition, which comes in handy when debugging mixed signal designs.

If you really need the extra time and speed, there’s always parallel SRAM. . .granted it would add cost.

6. rik says:

but hey, 128Kbyte SRAM is less then 5 euro, 4 euro something at farnell :)

• makomk says:

You might find that cheaper SRAM isn’t fast enough to keep up with the maximum sample rate…

7. Nikolay says:

Cool stuff. I’d like to create open source client for it.

• rsdio says:

I think that the OLS client already supports 8-bit DSO display.

• Ian says:

Yup, the client we’re using is GPL.

8. Nikolay says:

Yes, but the GUI is kind of … limited. Looking at the other LA software (comercial ones like DigiView, Saleae Logic, USBee, etc.) the GUI is much better. I realize the SUMP is just starting, and I wish to see it improved. What I’d like to do is an alternative to it. Even I started some time ago (using Qt), but unfortunately have no much free time right now. However, the market now is starving for those kind of tools and I believe that’s a good way to go. Wish you all the best.

9. Michel Stempin says:

FYI, here is a link to an open and full fledged DSO with all the bells and whistles:
– dual analog channel with AC/DC/GND coupling, 10 bits resolution, +/- 400 V input protection with 10x probes
– intermediate Voltage Gain controlled Amplifier (VGA) with 100 dB control voltage input, offering 10 sensitivity levels from 100 mV/div to 100 V/div
– 16 digital inputs + 16 digital outputs
– extension header for local keyboard/LCD/battery
– galvanic-isolated USB interface

http://www.soudez.be/joomla/content/view/12/27/lang,en/

Maybe something in-between this high-end DSO and the current low-cost Dangerous DSO design could be considered?

10. Christer Weinigel says:

I think that the big overshoot at the edges is due to you not compensating for the capacitance of the probe, you need a capacitive voltage divider in parallel with the resistive one. Something like the input stage described here:

http://zoo.weinigel.se/trac/public/wiki/Scope_Analog

Note, I really don’t know what I’m doing, instead I copied most of my stuff from a guy named Johann Glaser’s but his pages are gone by now, so you’ll have to make to with mine.

The page above is the analog design of for my attempt to build a 100MHz 250MSamples/s scope:

http://zoo.weinigel.se/trac/public/wiki/Scope

I’v actually come a bit further since this, I have connected this to the FPGA board which I’ve used to stream samples onto my PC. So I actually managed to plot data from the scope onto the screen. But I haven’t documented any of that yet.