App note: Using a microprocessor to configure Xilinx FPGAs via slave serial or selectMAP mode
Great app note from Xilinx on configuring their FPGA through slave serial and parallel selectMAP mode
This entry was posted in app notes and tagged app note, CPLD, FPGA, Xilinx.This application note describes a technique for configuring an FPGA from an embedded processor. Three common components are required: an embedded microprocessor, some non-volatile memory, and a CPLD. Cost, as well as real estate, can be reduced if the function of a dedicated configuration device, such as a PROM, can be integrated within these three components.Note: Some systems might not require a CPLD if the microprocessor has a sufficient number of general-purpose I/O (GPIO) pins available. For these systems, the Xilinx FPGA can be configured directly by the microprocessor.