Bus Blaster v4 free PCB build and test
Mikelelere verified the Bus Blaster v4 design.
I checked the board via the test program, and it successfully passed the tests (see the attached photographs). I’ve also succesfully used it to program a Coolrunner II CPLD board and a Lattice ISPMach128v CPLD, and I can confirm that the board is working flawlessly.
Bus Blaster is an experimental, high-speed JTAG debugger. Version 4 features an even larger CPLD to support an optional (and rarely used) feature of the new type of ARM debugging protocol (SVO feature of SWD).
We have no idea when v4 will be released. V4 will be more expensive than v2 because of the higher pincount CPLD and extra chips. v2 (or a variant) will continue to be available for $35.
Get your own handy Bus Blaster v2 for $35.
Via the forum.
This entry was posted in builds and tagged free pcb.
Comments
Would it be possible to shift all of the pins to one ‘IDE’ cable junction so to allow us to use old IDE cables to connect to other devices, or maybe a breakout board to tie them in as such.
Which pins do you mean? The extra pins on the side are IO breakouts for developers, only the main JTAG header need be used. Perhaps you mean with a missing key pin and correct sized shrouded header?
I’m holding out for a bus blaster V4 :-)
Though if it’s getting that much more expensive, it might be better to just get the jlink personal edition…
Were can I find the latest files for the bus blaster v4.x? I would like to get some boards made has the board been updated with the 1.8v reg?
They are all in SVN in the Bus Blaster folder. There is a latest board with a number of updates.
http://code.google.com/p/dangerous-prototypes-open-hardware/source/browse/#svn%2Ftrunk%2FBus_Blaster%2Fhardware
thanks