Free Model Foundry: open source CPLD/FPGA simulation models
Here’s a site we found containing open source simulation models for system level verification of CPLD/FPGA devices.
“Founded in 1995, Free Model Foundry (FMF) is dedicated to promoting standard modeling practices within the electrical engineering comunity. In particular, we support the use of VHDL, Verilog, and SystemVerilog modeling languages.
They believe in free, open source distribution of simulation and analysis models of electronic components. It promotes the development, distribution and sharing of functional simulation models (with timing) for board level components and open source behavioral models for proprietary IP.”
This entry was posted in code, CPLD, documentation, FPGA, open source, site and tagged libraries, Verilog, VHDL.
Comments
This site is cool. Also don’t forget this one:
http://opencores.org/
gauct