Workshop video #03: Bus Blaster JTAG debugger history
In this video Texas Instruments gets the Big Box award, and we discuss the evolution of the Bus Blaster JTAG debugger.
The Bus Blaster is our inexpensive, open source JTAG debugger based on the FTDI FT2232H UBS->serial chip. This chip has 2 JTAG interfaces and can program/debug two separate JTAG targets.
- Bus Blaster v1 used 5 discrete logic chips to do level translation between the FT2232 JTAG debugger chip at 3.3volts and the target chip at 1.2-3.3volts.
- v2/v2.5 replaced the expensive logic chips with a reprogrammable CPLD. We connected the unused secondary JTAG port on the FT2232 to the CPLD programming port. The buffer can be programed over USB without any extra hardware.
- v3 is a minor update of v2.5, fit for a case. We incremented to v3 because there is a slightly different connection between the FT2232 and CPLD. We moved the FT2232 synchronous clock output pin to a global clock pin on the CPLD. v2 and v3 bitstreams will not be compatible.
- Bus Blaster v4 adds a switch to toggle the secondary JTAG pins between the programming the buffer, and connecting to the external target. Bus Blaster v2/v3 supports most features of the new SWD reduced-wire JTAG interface. One feature, SVO, requires the UART hardware in the secondary JTAG port we use to program the buffer CPLD. Quick fix: add a switch. A larger CPLD is used because we now need to connect all the extra pins of the secondary JTAG port to the CPLD.
There is absolutely no estimated date of production for the new boards. v2.5 will probably be the only Bus Blaster available for the next year.
Pinnacle Studio 15 video editing software refused to render the whole video, this first part is what we could get. Pinnacle also has a 5x max speedup, so the soldering time-lapse was nearly 20 minutes. The second part, PCB assembly, will go up tomorrow using a new video editing craplication…This entry was posted in Bus Blaster, Videos and tagged Bus Blaster.