7400 competition entry: Analog comparator

in 7400 contest by DP | 1 comment

Joseph built an analog comparator for the Open 7400 Logic competition.

Using two NAND 3-input gates and a D-type flip-flop, he build a clocked analog comparator. After reviewing the internal composition of a CMOS NAND 3 gate he noticed that two of them connected in the right way make up a comparator. To make his own version he used a D-type flip-flop to save the output value from the gate before it resets on the next cycle. Schematic, as well as some logic gate theory, is available on his site.

Via the contact form.

This entry was posted in 7400 contest and tagged , .

Comments

  1. rsdio says:

    This one’s a contender. It didn’t look like much in the photo, but this is a very nice abuse of FET logic gates for analog purposes.

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