Bus Blaster v2 back in stock
Bus Blaster v2 JTAG debugger is back in stock at Seeed Studio.The cool thing about the Bus Blaster is that it uses a programmable logic chip as a buffer. It can imitate different types of programming hardware with a simple USB update.
This batch is a new revision (v2.5). It includes a button and LED connected to the CPLD breakout pins. The local power selection header (JP4) was also moved to the edge of the PCB.
You can get a Bus Blaster v2 for $34.95.
This entry was posted in Bus Blaster and tagged Bus Blaster v2, stock.
Comments
How’s v3 coming? My understanding is that it can support SWD and trace?
v2 supports SWD with the kt-link buffer, but v3 will also support the SWO (?) feature. The problem is we use the secondary JTAG interface to program the buffer in update mode. ktlink uses the serial UART pin (shard with JTAG pins) to receive the SWO channel data (or, as I recall….). We had to make a selector so it can be used for IO in normal mode, or switched to update the buffer.
V3 is in the queue, but not yet started. Maybe next spring/summer.
Think I will order another since my first got stolen in the mail amazingly lol
HI,
I would like to know if bus blaster + opencdo supports Xilinx Spartan/Virtex 6?
Thanks in advance!
Regards
OpenOCD is mostly for processors like ARM, MIPS, Intel, etc.
If Xilinx ISE exports SVF files for Virtex6, then you can probably (probably) play them into the FPGA with urJTAG and the Bus Blaster. I have not tested it (yet) though.
maybe http://www.amontec.com/jtagkey.shtml and see SVF Player optimized for JTAGkey and tested on Xilinx FPGA as Altera FPGA …
Thanks for clarification Ian!