Lattice announces Diamond release 1.3
Lattice Semiconductor has just announced Lattice Diamond® release 1.3, updating their FPGA design software environment. They write:
This release further builds on helping FPGA designers reach their goals for cost sensitive and low-power applications. In addition to its industry-leading Power Calculator, Lattice Diamond 1.3 software now aids migrating a design to a lower cost device as well as improving design resilience with clock jitter analysis. Other new software enhancements include support of complex multi-file simulation testbenches, a more intuitive synthesis constraint flow, and a significant speed-up of the download of large trace data and complex trigger configuration for on-chip debugging.
You can download your copy (1.8 GB) from the Lattice website.
This entry was posted in CPLD, FPGA, software and tagged CPLD, Diamond, FPGA, Lattice.
Recent Comments