STATUS UPDATE: Bus Blaster v2
We’re trying a new Monday post with status updates on new projects currently in production. This will cover project development, and gritty details like last minutes changes and production problems.
Bus Blaster v2 is going to rock! The design is so flexible and fun, we can’t believe it wasn’t the standard FT2232 JTAG debugger design already. It’s a JTAG debugger that can clone many other debuggers, and it’s an all-in-one CPLD development board. And it’s cheap!
V1 had a bunch of expensive logic chips that set the design in stone. V2 has a reprogrammable logic chip (CPLD) that can be updated on the fly. Have an app that’s only compatible with a simple JTAGkey debugger? Program the JTAGkey buffer logic. Want to try the proposed Serial Wide Debug support in OpenOCD and urJTAG? Program the KT-link buffer.
A patch that supports v2′s self-programming feature was accepted by urJTAG and will be included in the next release. Until then, we have a patched nightly compile that can be used to switch buffer logic.
The Bus Blaster v2 was first delayed when it didn’t make the last production before the Chinese Spring holiday, and further because of a last-minute PCB revision to remove the defective target present LED. Most recently it was delayed due to a driver problem on the manufacturing test computer.
Bus Blaster v2 is back on track and due any day. We’ll follow up later this week with solid details when we hear more.CPLD, dev boards, Development, Status update and tagged manufacturing, updates.