Bus Blaster v2 testing

in Bus Blaster, Development by Ian | 10 comments

We’ve just completed verification of the Bus Blaster v2 JTAG debugger. V2 is much more flexible than v1, and uses a programmable logic chip (CPLD) for the buffer. The logic chips in v1 were expensive to source and place, but v2 uses a $1 CPLD with a bunch less pins to solder and inspect. Bus Blaster v1 will be available soon in limited production, then we’ll switch to v2.

The CPLD can be programmed to resemble just about any existing FT2232-based JTAG debugger. Proprietary software needs some funky connection to a JTAG device? No problem, just implement it in the CPLD.

Our first CPLD implementation is a clone of the Amontec JTAGkey. This is a common debugger that’s copied in a lot of projects, like OpenMoko. Eventually we’d like to have a full library of different interface clones that can be used with Bus Blaster v2.

We used Bus Blaster v1 to program the Bus Blaster v2 CPLD, though the goal is to make v2 self-programming. The CPLD is connected to the secondary JTAG interface on the FT2232 so it can be done, in theory. The problem is that our loader software doesn’t support the B interface yet. Robots and Tornado are currently looking into it.

We’re going to start the Bus Blaster v2 production process. We hope to have the ability to upgrade the CPLD without an external programmer before launch, but if not that’s ok. The current interface is sufficient for most uses, and it clones the Bus Blaster v1 connections. The great thing about open source is that anyone can contribute these features later, we don’t have to have a complete project from the beginning.

You might notice the fly wire from C1 to C19 – this happened because the supply pin wasn’t fully connected in the Eagle schematic. Simple problem to fix in the v2a production version.

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Comments

  1. DrF says:

    Looking good, I’ll be buying when it comes into production :)

  2. blipton says:

    I’ve always wondered what the difference in jtag dongles was..

    For example, what is the difference between a Amontec JTAGkey and a Segger J-Link?
    http://www.segger.com/cms/jlink.html

    Or a Green Hills Probe and an Actel Flash Pro 4
    http://www.ghs.com/products/supertraceprobe.html
    http://www.actel.com/products/hardware/program_debug/flashpro/default.aspx

    They all seem to vary wildly in price, support different processors, and software.

    Speed I can understand, but what makes up the difference?

    • Ian says:

      A lot, but not all, of them are FT2232-based. Check out the OpenOCD project config files for details on each. The difference is:
      1. Buffer front end (or lack of) between the FT2232 and JTAG target (the construction of the logic and pin connections. Also the voltage range: 5.0volt-1.2volt, or somewhere in between like the Bus Blaster’s 3.3volts to 1.2volts)
      2. The USB VID/PID and descriptor programmed into the FT2232 EEPROM

      The Bus Blaster v2 gives us complete control over both, so it can be hacked to appear as a lot of these devices. The EEROM can be programmed with FTDI’s utilities, and the CPLD can connect any pin of JTAG A port to the JTAG header. The only thing BBv2 doesn’t support is stuff that needs JTAG B, because it connects to the CPLD there (though you still might be able to use the USB->serial converter on JTAG B while using the BBv2).

  3. sqkybeaver says:

    congratulations guys,
    i will be looking into finding support for the silicon labs chips, as soon as i get one.

  4. MichaelZ says:

    Hmmm, the CPLD is upgradeable to a XC2C64A-VQ44…evil deeds a brewing…

    • Ian says:

      I have a couple here. We don’t need the space for the programmer, and it saves a buck to use the 32 cell version.

      It would make a much better “mini” dev-board to have more macrocells.

      It might also make it easier to add a combined JTAG front-end and Logic Analyzer front end that is selectable from the FT2232H spare pins (maybe we can do that already, I have not looked at the requirements).

      • tayken says:

        So we can upgrade it ourselves maybe?

      • Ian says:

        Sure, it’s a pretty easy chip to solder, and there maybe an ‘education’ version with the larger chip if there’s demand. If this is a popular project, the 64 cell version may become the default because the price difference is much smaller at higher quantities.

      • tayken says:

        The only thing that bothers me is the desoldering part. I think that people may want the 64 cell version even if they will not do any type of development work.

  5. ian says:

    test comment

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