I obviously can’t speak for others but I would be willing to pay extra to have full USB 2.0 speed with a FT2232H. I think having the ability to stream data a few Mhz and lower to your PC would be worth the extra few dollars.

Jack.

I think we should try to make it as simple and cost effective as possible for the first revision. The Spartan 3E-250 has 216k of block ram which would give us 6K samples. For most purposes that is enough… We could easily drop in a Spartan 3E-500 which would give us 11k samples at 32 channels. We can also try to use distributed ram or only provide 16 channels if we really want to provide more samples. So for the first revision I would suggest we forgo the SRAM, SDRAM, or DRAM. I’ve made designs with SDRAM and DRAM in the past with mixed results. I was never able to get DRAM to work properly with a double layer board. SDRAM is possible on a two layer board but I think we should save that for a later revision. I think most people will be very happy with 6K samples. I only mentioned SDRAM because I think that will be the key to making it function in realtime…

So if you guys agree to forgo the external memory then that leaves the question of providing a voltage buffer for the inputs. Do you feel it is important? The Spartan 3E can handle up to 3.3V by itself but will be damaged by anything higher. I have a buffer design in place already, http://www.gadgetfactory.net/gf/project/bpw5009-buffer/ based on the 16 bit M74LCX16245. This would allow voltages up to 7V and is 4.5ns and would require only two parts.

I’m down for collaborating on this, but I’m not sure we could accomplish a sale price of $30… The spartan 3e chip is $13 and the ftdi2232h is $4 or $5… The power supply will probably add $3-6. PCB will cost $2-4. These numbers are off the top of my head and might be off.

Jack.

I designed a DRAM controller for a project in school but that was some time ago. Opencores has a few memory controllers you can just drop into the design. Also many of the FPGA/CPLD vendors offer free memory controllers you can integrate into your design, the learning curve is not bad but it is definitely time consuming.

DRAM is indeed cheaper, and I understand it’s not difficult to implement a controller in FPGA or CPLD (I’ve read a few nice app sheets). But again, way beyond what I can knock-up in a weekend on a 2-layer board.

There’s sump host implementations for a bunch of different FPGA DEV boards. My existing plan was to find a good one with highly-available parts, strip it down, and make the cheapest, simplest 2-sided PCB I can. If it floats, and I can stand the dev tools (Xilinx 10.1 was a nightmare), then I’d plan a version 2. My price goal was around $30, shipped, I worry more is on par with a full FPGA dev board.

If there’s serious interest in collaboration, I’ll start a new board in the forum and we can start looking at parts.

No buffers are used to interface with SRAM, you wire the RAM directly to the FPGA\CPLD. Sometimes series termination resistors are used to reduce ring. SDRAM or DRAM could also be used.

The FPGA used in the butterfly only has 216k of dedicated block ram on the device. It would be cheaper to use DRAM instead of SRAM but would need a much more complicated memory controller core on the FPGA, $2-3 for 16Meg: http://www.mouser.com/issi/

Lots of fun options to choose from, it seems it could be done for less then $75 sales price for hardware

As I recall from my previous journey into the world of SRAM, speeds go up to around 100MHz. They are 8,16,32 bits wide, and around 18 address lines for a 4Mbit (256K sample) chip.

Like: http://www.mouser.com/ProductDetail/Cypress-Semiconductor/CY7C1041D-10ZSXI/?qs=sGAEpiMZZMs6Aik9Fp479rPSFu914cdUmPOXn5OlesE%3d
9Mbit/166MHz: http://www.mouser.com/ProductDetail/Cypress-Semiconductor/CY7C1360C-166AXI/?qs=sGAEpiMZZMs6Aik9Fp479rPSFu914cdUuGgsK3ZVMt8%3d

If I were doing this on my own, here’s the things that give me pause. But together we might prevail :)
That’s a lot of pins to route, with the expectation of high-speed signaling.
Those are some expensive chips.
What kind of buffers are fast enough to interface the SRAM at 166Mhz? How much do they cost?
How much ram is enough? I’m a fairly active prototyper and I never use more than 4K samples (the first screen of output) to debug issues. I have no idea what other use profiles require in terms of storage.

Here’s my previous dev board for the LA (using the 573): http://hackaday.com/2008/12/11/how-to-programmable-logic-devices-cpld/